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INTEGRATED CIRCUITS
80C554/87C554
80C51 8-bit microcontroller - 6 clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
Product data Supersedes data of 2000 Nov 10 2003 Jan 28
Philips Semiconductors
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
8DESCRIPTION
This data sheet describes the 6 clock version of the 8xC554. This device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C554 has the same instruction set as the 80C51. Three versions of the derivative exist:
* 80C51 central processing unit * 16k x 8 EPROM expandable externally to 64 kbytes * An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
FEATURES
* 80C554--ROMless version * 87C554--16 kbytes EPROM
The 87C554 contains a 16k x 8 non-volatile EPROM, a 512 x 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, four-priority-level, nested interrupt structure, an 7-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8xC554 can be expanded using standard TTL compatible memories and logic. In addition, the 8xC554 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. Optionally, the ADC can be operated in Idle mode. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With an 8-MHz crystal, 58% of the instructions are executed in 0.75 s and 40% in 1.5 s. Multiply and divide instructions require 3 s.
* Two standard 16-bit timer/counters * 512 x 8 RAM, expandable externally to 64 kbytes * Capable of producing eight synchronized, timed outputs * A 10-bit ADC with seven multiplexed analog inputs * Fast 8-bit ADC option - 9 S at 16 MHz * Two 8-bit resolution, pulse width modulation outputs * Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
* I2C-bus serial I/O port with byte oriented master and slave
functions
* On-chip watchdog timer * Extended temperature ranges * Full static operation - 0 to 16 MHz * Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and
4.5 V to 5.5 V (8 to 16 MHz) commercial temperature
* Security bits:
- ROM - 2 bits - OTP/EPROM - 3 bits
* Four interrupt priority levels * 15 interrupt sources * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
* Power control modes
- Clock can be stopped and resumed - Idle mode - Power down mode
* Second DPTR register * EMI reduction - 6 clock operation and ALE inhibit * Programmable I/O pins * Wake-up from power-down by external interrupts * Software reset * Power-on detect reset * ADC charge pump disable * ONCE mode * ADC active in Idle mode
2003 Jan 28
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853-2408 29338
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
ORDERING INFORMATION
OTP/EPROM P87C554SBBD P87C554SFBD ROMless P80C554SBBD P80C554SFBD TEMPERATURE C AND PACKAGE 0 to +70, Low Profile Quad Flat Package -40 to +85, Low Profile Quad Flat Package FREQ. (MHz) 16 16 DRAWING NUMBER SOT314-2 SOT314-2
PART NUMBER DERIVATION
DEVICE NUMBER P87C554 OTP P80C554 ROMless S = 16 MHz OPERATING FREQUENCY MAX TEMPERATURE RANGE B= 0_C to 70_C F = -40_C to +85_C PACKAGE BD=64L LQFP
BLOCK DIAGRAM
T0 3 T1 3 INT0 3 INT1 3 VDD VSS PWM0 PWM1 AVSS
AVDD
AVREF ADC0-7 SDA
SCL 1 1
-+
STADC
5
XTAL1 XTAL2 EA ALE PSEN 3 3 RD 0 AD0-7 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES 16 WR T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY 16k x 8 OTP/ROM DATA MEMORY 512 x 8 RAM DUAL PWM ADC SERIAL I2C PORT
CPU
80C51 CORE EXCLUDING ROM/RAM
8-BIT INTERNAL BUS
T2 16-BIT TIMER/ EVENT COUNTERS
16
T2 16-BIT COMPARATORS WITH REGISTERS
COMPARATOR OUTPUT SELECTION
T3 WATCHDOG TIMER
3 P0 P1 P2 P3 TxD
3 RxD P5 P4 CT0I-CT3I
1
1 T2 RT2
1
4 CMSR0-CMSR5 CMT0, CMT1 RST EW
0 1 2
ALTERNATE FUNCTION OF PORT 0 ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2
3 4 5
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
SU00951
2003 Jan 28
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
PIN CONFIGURATIONS Plastic Quad Flat Pack pin functions
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Function AVDD P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 VDD STADC PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 Pin 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. Function P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA P3.0/RxD P3.1/TxD Pin 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. Function P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VSS P2.0/A08 P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 Pin 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. Function P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref- AVref+ AVSS
48
33
49
32
LQFP64
64
17
1
16
SU01444
LOGIC SYMBOL
VSS VDD XTAL1 XTAL2 EA/VPP ALE/PROG PSEN AVSS AVDD AVref+ AVref- STADC PWM0 PWM1
PORT 0
LOW ORDER ADDRESS AND DATA BUS
ADC0-7 PORT 5
CT0I CT1I CT2I CT3I T2 RT2 SCL SDA
PORT 2
PORT 1
HIGH ORDER ADDRESS AND DATA BUS
CMSR0-5 PORT 4 RxD/DATA TxD/CLOCK INT0 INT1 T0 T1 WR RD
CMT0 CMT1 RST EW
PORT 3
SU00210
2003 Jan 28
4
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
PIN DESCRIPTION
PIN NO. MNEMONIC VDD STADC PWM0 PWM1 EW P0.0-P0.7 LQFP 9 10 11 12 13 54-61 TYPE I I O O I I/O NAME AND FUNCTION Digital Power Supply: Positive voltage power supply pin during normal operation, idle and power-down mode. Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). Pulse Width Modulation: Output 0. Pulse Width Modulation: Output 1. Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during programming and to output the code byte during verification. Port 1: 8-bit I/O port. Alternate functions include: (P1.0-P1.5): Programmable I/O port pins. (P1.6, P1.7): Open drain port pins. CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input. RT2 (P1.5): T2 timer reset signal. Rising edge triggered. SCL (P1.6): Serial port clock line I2C-bus. SDA (P1.7): Serial port data line I2C-bus. Port 1 has four modes selected on a per bit basis by writing to the P1M1 and P1M2 registers as follows: P1M1.x P1M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration; default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. P2.0-P2.7 43-50 I/O Port 2: 8-bit programmable I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on P2.1, through A13 on P2.5. Port 2 has four output modes selected on a per bit basis by writing to the P2M1 and P2M2 registers as follows: P2M1.x P2M2.x Mode Description 0 0 Pseudo-bidirectional (standard c51 configuration; default) 0 1 Push-Pull 1 0 High impedance 1 1 Open drain Port 3: 8-bit programmable I/O port. Alternate functions include: RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. Port 3 has four modes selected on a per bit basis by writing to the P3M1 and P3M2 registers as follows: P3M1.x 0 0 1 1 P3M2.x 0 1 0 1 Mode Description Pseudo-bidirectional (standard c51 configuration; default) Push-Pull High impedance Open drain
P1.0-P1.7
23-30 23-28 29-30 23-26 27 28 29 30
I/O I/O I/O I I I I/O I/O
P3.0-P3.7
31-38 31 32 33 34 35 36 37 38
I/O
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
PIN DESCRIPTION (Continued)
PIN NO. MNEMONIC P4.0-P4.7 LQFP 14-21 14-19 20, 21 TYPE I/O O O NAME AND FUNCTION Port 4: 8-bit programmable I/O port. Alternate functions include: CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as follows: P4M1.x 0 0 1 1 P5.0-P5.6 RST XTAL1 XTAL2 VSS PSEN ALE/PROG 2-8 22 40 39 41-42 51 52 I I/O I O I O O P4M2.x 0 1 0 1 Mode Description Pseudo-bidirectional (standard c51 configuration; default) Push-Pull High impedance Open drain
Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Seven input channels to the ADC. Reset: Input to reset the 87C554. It also provides a reset pulse as output when timer T3 overflows. Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. Digital ground. Program Store Enable: Active-low read strobe to external program memory. Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG) during EPROM programming. External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 16,384. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. Analog to Digital Conversion Reference Resistor: Low-end. Analog to Digital Conversion Reference Resistor: High-end. Analog Ground
EA/VPP
53
I
AVREF- AVREF+ AVSS
62 63 64
I I I
AVDD 1 I Analog Power Supply NOTE: 1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS - 0.5 V, respectively.
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 1.
SYMBOL
87C554 Special Function Registers
DESCRIPTION DIRECT ADDRESS BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE
ACC* ADCH# ADCON# AUXR AUXR1 B* CTCON# CTH3# CTH2# CTH1# CTH0# CMH2# CMH1# CMH0# CTL3# CTL2# CTL1# CTL0# CML2# CML1# CML0# DPTR: DPH DPL
Accumulator A/D converter high A/D control Auxiliary Auxiliary B register Capture control Capture high 3 Capture high 2 Capture high 1 Capture high 0 Compare high 2 Compare high 1 Compare high 0 Capture low 3 Capture low 2 Capture low 1 Capture low 0 Compare low 2 Compare low 1 Compare low 0 Data pointer (2 bytes): Data pointer high Data pointer low
E0H C6H C5H 8EH A2H F0H EBH CFH CEH CDH CCH CBH CAH C9H AFH AEH ADH ACH ABH AAH A9H
E7
E6
E5
E4
E3
E2
E1
E0
00H xxxxxxxxB
ADC.1 - ADC8 F7 CTN3
ADC.0 - AIDL F6 CTP3
ADEX - SRST F5 CTN2
ADCI - GF2 F4 CTP2
ADCS - WUPD F3 CTN1
AADR2 LVADC O F2 CTP1
AADR1 EXTRAM - F1 CTN0
AADR0 A0 DPS F0 CTP0
xx000000B xxxxx110B 000000x0B 00H 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB 00H 00H 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB 00H 00H 00H
83H 82H AF AE EAD EE ECM2 BE PAD FE PADH PCM2 PCM2H ADC6 C6 CMT0 B6 WR A6 A14 96 SCL 86 AD6 AD ES1 ED ECM1 BD PS1 FD PS1H PCM1 PCM1H ADC5 C5 CMSR5 B5 T1 A5 A13 95 RT2 85 AD5 AC ES0 EC ECM0 BC PS0 FC PS0H PCM0 PCM0H ADC4 C4 CMSR4 B4 T0 A4 A12 94 T2 84 AD4 AB ET1 EB ECT3 BB PT1 FB PT1H PCT3 PCT3H ADC3 C3 CMSR3 B3 INT1 A3 A11 93 CT3I 83 AD3 AA EX1 EA ECT2 BA PX1 FA PX1H PCT2 PCT2H ADC2 C2 CMSR2 B2 INT0 A2 A10 92 CT2I 82 AD2 A9 ET0 E9 ECT1 B9 PT0 F9 PT0H PCT1 PCT1H ADC1 C1 CMSR1 B1 TXD A1 A9 91 CT1I 81 AD1 A8 EX0 E8 ECT0 B8 PX0 F8 PX0H PCT0 PCT0H ADC0 C0 CMSR0 B0 RXD A0 A8 90 CT0I 80 AD0
00H 00H
IEN0*#
Interrupt enable 0
A8H
EA EF
00H
IEN1*#
Interrupt enable 1
E8H
ET2 BF
00H
IP0*#
Interrupt priority 0
B8H
- FF
x0000000B
IP0H IP1*# IP1H P5#
Interrupt priority 0 high Interrupt priority1 Interrupt priority 1 high Port 5
B7H F8H F7H C4H
- PT2 PT2H ADC7 C7
x0000000B 00H 00H xxxxxxxxB
P4#*
Port 4
C0H
CMT1 B7
FFH
P3*
Port 3
B0H
RD A7
FFH
P2*
Port 2
A0H
A15 97
FFH
P1*
Port 1
90H
SDA 87
FFH
P0*
Port 0
80H
AD7
FFH
2003 Jan 28
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SYMBOL
DESCRIPTION
DIRECT ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB
RESET VALUE
P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 P4M1 P4M2 PCON PSW PWMP# PWM1# PWM0# RTE# S0ADDR S0ADEN S0BUF
Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Port 4 output mode 1 Port 4 output mode 2 Power control Program status word PWM prescaler PWM register 1 PWM register 0 Reset/toggle enable Serial 0 slave address Slave address mask Serial 0 data buffer
92H 93H 94H 95H 9AH 9BH 9CH 9DH 87H D0H FEH FDH FCH EFH F9H B9H 99H 9F 9E SM1 9D SM2 9C REN SLAVE ADDRESS 9B TB8 9A RB8 99 TI 98 RI GC TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40 SMOD1 CY SMOD0 AC POF FO WLE RS1 GF1 RS0 GFO OV PD F1 IDL P
xx000000B xx000000B 00H 00H 00H 00H 00H 00H 00x00000B 00H 00H 00H 00H 00H 00H 00H xxxxxxxxB
S0CON* S1ADR# SIDAT# S1STA#
Serial 0 control Serial 1 address Serial 1 data Serial 1 status
98H DBH DAH D9H
SM0/FE
00H 00H 00H
SC4 DF
SC3 DE ENS1
SC2 DD STA
SC1 DC ST0
SC0 DB SI
0 DA AA
0 D9 CR1
0 D8 CR0
F8H
SICON#* SP STE# TH1 TH0 TL1 TL0 TMH2# TML2# TMOD
Serial 1 control Stack pointer Set enable Timer high 1 Timer high 0 Timer low 1 Timer low 0 Timer high 2 Timer low 2 Timer mode
D8H 81H EEH 8DH 8CH 8BH 8AH EDH ECH 89H
CR2
00H 07H
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
C0H 00H 00H 00H 00H 00H 00H
GATE 8F
C/T 8E TR1 T2IS0 CE CMI2
M1 8D TF0 T2ER CD CMI1
M0 8C TR0 T2B0 CC CMI0
GATE 8B IE1 T2P1 CB CTI3
C/T 8A IT1 T2P0 CA CTI2
M1 89 IE0 T2MS1 C9 CTI1
M0 88 IT0 T2MS0 C8 CTI0
00H
TCON* TM2CON#
Timer control Timer 2 control
88H EAH
TF1 T2IS1 CF
00H 00H
TM2IR#* T3#
Timer 2 int flag reg Timer 3
C8H FFH
T20V
00H 00H
* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.
2003 Jan 28
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. The minimum and maximum high and low times specified in the data sheet must be observed.
VDD
VDD + 2.2 F 8XC554
RESET
A reset is accomplished by either (1) externally holding the RST pin high for at least two machine cycles (12 oscillator periods) or (2) internally by an on-chip power-on detect (POD) circuit which detects VCC ramping up from 0 V. To insure a good external power-on reset, the RST pin must be high long enough for the oscillator to start up (normally a few milliseconds) plus two machine cycles. The voltage on VDD and the RST pin must come up at the same time for a proper startup. For a successful internal power-on reset, the VCC voltage must ramp up from 0 V smoothly at a ramp rate greater than 5 V/100 ms. The RST line can also be pulled HIGH internally by a pull-up transistor activated by the watchdog timer T3. The length of the output pulse from T3 is 3 machine cycles. A pulse of such short duration is necessary in order to recover from a processor or system fault as fast as possible. Note that the short reset pulse from Timer T3 cannot discharge the power-on reset capacitor (see Figure 2). Consequently, when the watchdog timer is also used to set external devices, this capacitor arrangement should not be connected to the RST pin, and a different circuit should be used to perform the power-on reset operation. A timer T3 overflow, if enabled, will force a reset condition to the 8xC554 by an internal connection, independent of the level of the RST pin. A reset may be performed in software by setting the software reset bit, SRST (AUXR1.5).
RST
RRST
SU00953
Figure 2. Power-On Reset
LOW POWER MODES Stop Clock Mode
The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while some of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
VDD
OVERFLOW TIMER T3 SCHMITT TRIGGER
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated. Either a hardware reset or external interrupt can be used to exit from Power Down. The Wake-up from Power-down bit, WUPD (AUXR1.3) must be set in order for an external interrupt to cause a wake-up from power-down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).
RST ON-CHIP RESISTOR
RESET CIRCUITRY
RRST
SU00952
Figure 1. On-Chip Reset Configuration
2003 Jan 28
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Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 2. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data PORT 4 Data Data Data Data PWM0/ PWM1 High High High High
With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 8xC554 rises from 0 to 5 V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3 V for the POF to remain unaffected by the VCC level.
Reduced EMI Mode
The ALE-Off bit, AO (AUXR.0) can be set to disable the ALE output. It will automatically become active when required for external memory accesses and resume to the OFF state after completing the external memory access.
Design Consideration
* When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
7 PCON (87H)
6
5 POF
4 WLE
3 GF1
2 GF0
1 PD
0 IDL (LSB)
SMOD1 SMOD0 (MSB)
BIT PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0
SYMBOL SMOD1 SMOD0 POF WLE GF1 GF0 PD IDL
FUNCTION Double Baud rate bit. When set to logic 1, the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2, or 3. Selects SM0/FE for SCON.7 bit. Power Off Flag Watchdog Load Enable. This flag must be set by software prior to loading timer T3 (watchdog timer). It is cleared when timer T3 is loaded. General-purpose flag bit. General-purpose flag bit. Power-down bit. Setting this bit activates the power-down mode. It can only be set if input EW is high. Idle mode bit. Setting this bit activates the Idle mode.
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00X00000).
SU00954
Figure 3. Power Control Register (PCON)
2003 Jan 28
10
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Expanded Data RAM Addressing
The 8xC554 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes expanded RAM (EXTRAM). The four segments are: 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. 4. The 256-bytes expanded RAM (ERAM, 00H - FFH) are indirectly accessed by move external instruction, MOVX, and with the EXTRAM bit cleared, see Figure 4. The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For example: MOV 0A0H,#data accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0,#data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). The ERAM can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory is physically located on-chip, logically occupies the first 256-bytes of external data memory. With EXTRAM = 0, the EXTRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ERAM will not affect ports P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during expanded RAM addressing. For example, with EXTRAM = 0, MOVX @R0,#data where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e., 0100H to FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. Refer to Figure 5. With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an 8-bit address multiplexed with data on Port 0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a 16-bit address. Port 2 outputs the high-order eight address bits (the contents of DPH) while Port 0 multiplexes the low-order eight address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will generate either read or write signals on P3.6 (#WR) and P3.7 (#RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM address space.
AUXR
Address = 8EH Not Bit Addressable -- Bit: 7 -- 6 -- 5 -- 4 -- 3 LVADC 2 EXTRAM 1 AO 0
Reset Value = xxxx x110B
Symbol AO
Function Disable/Enable ALE AO Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency. 1 ALE is active only during a MOVX or MOVC instruction. Internal/External RAM (00H - FFH) access using MOVX @Ri/@DPTR EXTRAM Operating Mode 0 Internal ERAM (00H-FFH) access using MOVX @Ri/@DPTR 1 External data memory access. Enable A/D low voltage operation LVADC 0 1 Operating Mode Turns off A/D charge pump. Turns on A/D charge pump. Required for operation below 4V.
EXTRAM
LVADC
--
Not implemented, reserved for future use*.
NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00979A
Figure 4. AUXR: Auxiliary Register
2003 Jan 28
11
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
FF
FF
FF
FFFF
UPPER 128 BYTES INTERNAL RAM
SPECIAL FUNCTION REGISTER
EXTERNAL DATA MEMORY
ERAM 256 BYTES
80
80
LOWER 128 BYTES INTERNAL RAM 0100 0000
00
00
00
SU00980
Figure 5. Internal and External Data Memory Address Space with EXTRAM = 0
Dual DPTR
The dual DPTR structure (see Figure 6) is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. The DPS bit status should be saved by software when switching between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero. This allows the DPS bit to be quickly toggled simply by executing an INC AUXR1 instruction without affecting the other bits. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR
DPS BIT0 AUXR1
MOV A, @ A+DPTR MOVX A, @ DPTR
DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY
MOVX @ DPTR , A JMP @ A + DPTR
SU00745A
Figure 6.
The data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the SFRs. See application note AN458 for more details.
2003 Jan 28
12
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
AUXR1
Address = A2H Not Bit Addressable ADC8 Bit: 7 AIDL 6 SRST 5 GF2 4 WUPD 3 0 2 -- 1 DSP 0
Reset Value = 0000 00x0B
Symbol DPS
Function Data Pointer Switch--switches between DPRT0 and DPTR1. DPS Operating Mode 0 DPTR0 1 DPTR1 Enable wakeup from powerdown. General Purpose Flag--set and cleared by the user. Software Reset Enables the ADC during idle mode. ADC Mode Switch--switches between 10-bit conversion and 8-bit conversion. ADC8 0 1 Operating Mode 10-bit conversion (50 machine cycles) 8-bit conversion (24 machine cycles)
WUPD GF2 SRST AIDL ADC8
NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01081
Figure 7. AUXR1: DPTR Control Register
2003 Jan 28
13
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Enhanced UART
The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM0 and the function of S0CON.7 is determined by PCON.6 (SMOD0) (see Figure 8). If SMOD0 is set then S0CON.7 functions as FE. S0CON.7 functions as SM0 when SMOD0 is cleared. When used as FE S0CON.7 can only be cleared by software. Refer to Figure 9. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using S0CON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4
hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in S0CON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 10. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.
Reset Value = 0000 0000B
TB8 3
RB8 2
Tl 1
Rl 0
7 6 (SMOD0 = 0/1)*
Symbol FE SM0 SM1
Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/6 variable fOSC/32 or fOSC/16 variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN TB8 RB8 Tl Rl
NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency
SU01445
Figure 8. S0CON: Serial Port Control Register
2003 Jan 28
14
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98H)
SMOD1
SMOD0
POF
WLE
GF1
GF0
PD
IDL
PCON (87H)
0 : S0CON.7 = SM0 1 : S0CON.7 = FE
SU00982
Figure 9. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0 1 1
SM1 1 0
SM2 1
REN 1
TB8 X
RB8
TI
RI
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 10. UART Multiprocessor Communication, Automatic Address Recognition Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 Slave 1 SADDR = SADEN = Given = 1100 0000 1111 1110 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
2003 Jan 28
15
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave 1
Either or both of these overflows can be programmed to request an interrupt. In both cases, the interrupt vector will be the same. When the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and flag T20V (TM2IR) is set when TMH2 overflows. These flags are set one cycle after an overflow occurs. Note that when T20V is set, T2B0 will also be set. To enable the byte overflow interrupt, bits ET2 (IEN1.7, enable overflow interrupt, see Figure 11) and T2IS0 (TM2CON.6, byte overflow interrupt select) must be set. Bit TWB0 (TM2CON.4) is the Timer T2 byte overflow flag. To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable overflow interrupt) and T2IS1 (TM2CON.7, 16-bit overflow interrupt select) must be set. Bit T2OV (TM2IR.7) is the Timer T2 16-bit overflow flag. All interrupt flags must be reset by software. To enable both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two interrupt service routines are required. A test on the overflow flags indicates which routine must be executed. For each routine, only the corresponding overflow flag must be cleared. Timer T2 may be reset by a rising edge on RT2 (P1.5) if the Timer T2 external reset enable bit (T2ER) in T2CON is set. This reset also clears the prescaler. In the idle mode, the timer/counter and prescaler are reset and halted. Timer T2 is controlled by the TM2CON special function register (see Figure 12). Timer T2 Extension: When a 6-MHz oscillator is used, a 16-bit overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms, depending on the prescaler division ratio; i.e., the maximum cycle time is approximately 0.5 seconds. In applications where cycle times are greater than 0.5 seconds, it is necessary to extend Timer T2. This is achieved by selecting fosc/12 as the clock source (set T2MS0, reset T2MS1), setting the prescaler division ration to 1/8 (set T2P0, set T2P1), disabling the byte overflow interrupt (reset T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The following software routine is written for a three-byte extension which gives a maximum cycle time of approximately 2400 hours. OVINT: PUSH PUSH INC MOV JNZ INC MOV JNZ INC INTEX: CLR POP POP RETI ACC PSW TIMEX1 ;save accumulator ;save status ;increment first byte (low order) ;of extended timer
Slave 2
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are trended as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. Timer T2 Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH byte) and TML2 (LOW byte). The 16-bit timer/counter can be switched off or clocked via a prescaler from one of two sources: fOSC/6 or an external signal. When Timer T2 is configured as a counter, the prescaler is clocked by an external signal on T2 (P1.4). A rising edge on T2 increments the prescaler, and the maximum repetition rate is one count per machine cycle (0.5 MHz with a 12-MHz oscillator). The maximum repetition rate for Timer T2 is twice the maximum repetition rate for Timer 0 and Timer 1. T2 (P1.4) is sampled at S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising edge is detected when T2 is LOW during one sample and HIGH during the next sample. To ensure that a rising edge is detected, the input signal must be LOW for at least 1/2 cycle and then HIGH for at least 1/2 cycle. If a rising edge is detected before the end of S2P1, the timer will be incremented during the following cycle; otherwise it will be incremented one cycle later. The prescaler has a programmable division factor of 1, 2, 4, or 8 and is cleared if its division factor or input source is changed, or if the timer/counter is reset. Timer T2 may be read "on the fly" but possesses no extra read latches, and software precautions may have to be taken to avoid misinterpretation in the event of an overflow from least to most significant byte while Timer T2 is being read. Timer T2 is not loadable and is reset by the RST signal or by a rising edge on the input signal RT2, if enabled. RT2 is enabled by setting bit T2ER (TM2CON.5). When the least significant byte of the timer overflows or when a 16-bit overflow occurs, an interrupt request may be generated.
A,TIMEX1 INTEX ;jump to INTEX if ;there is no overflow TIMEX2 ;increment second byte A,TIMEX2 INTEX ;jump to INTEX if there is no overflow TIMEX3 ;increment third byte (high order) T2OV PSW ACC ;reset interrupt flag ;restore status ;restore accumulator ;return from interrupt
Timer T2, Capture and Compare Logic: Timer T2 is connected to four 16-bit capture registers and three 16-bit compare registers. A capture register may be used to capture the contents of Timer T2 when a transition occurs on its corresponding input pin. A compare register may be used to set, reset, or toggle port 4 output pins at certain pre-programmable time intervals. The combination of Timer T2 and the capture and compare logic is very powerful in applications involving rotating machinery, automotive injection systems, etc. Timer T2 and the capture and compare logic are shown in Figure 13.
2003 Jan 28
16
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 IEN1 (E8H) ET2 (MSB) BIT IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0
6 ECM2
5 ECM1
4 ECM0
3 ECT3
2 ECT2
1 ECT1
0 ECT0 (LSB)
Reset Value = 00H
SYMBOL ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0
FUNCTION Enable Timer T2 overflow interrupt(s) Enable T2 Comparator 2 interrupt Enable T2 Comparator 1 interrupt Enable T2 Comparator 0 interrupt Enable T2 Capture register 3 interrupt Enable T2 Capture register 2 interrupt Enable T2 Capture register 1 interrupt Enable T2 Capture register 0 interrupt
SU01083
Figure 11. Timer T2 Interrupt Enable Register (IEN1)
7 TM2CON (EAH) T2IS1 (MSB) BIT TM2CON.7 TM2CON.6 TM2CON.5 TM2CON.4 TM2CON.3 TM2CON.2
6 T2IS0
5 T2ER
4 T2BO
3 T2P1
2 T2P0
1 T2MS1
0 T2MS0 (LSB)
Reset Value = 00H
SYMBOL TSIS1 T2IS0 T2ER T2BO T2P1 T2P0 T2P1 0 0 1 1
FUNCTION Timer T2 16-bit overflow interrupt select Timer T2 byte overflow interrupt select Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising edge on RT2 (P1.5). Timer T2 byte overflow interrupt flag Timer T2 prescaler select T2P0 0 1 0 1 Timer T2 Clock Clock source Clock source/2 Clock source/4 Clock source/8
TM2CON.1 TM2CON.0
T2MS1 T2MS0
Timer T2 mode select Mode Selected Timer T2 halted (off) T2 clock source = fOSC/6 Test mode; do not use T2 clock source = pin T2
SU01446
T2MS1 T2MS0 0 0 1 1 0 1 0 1
Figure 12. T2 Control Register (TM2CON)
2003 Jan 28
17
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
CT0I
INT
CT1I
INT
CT2I
INT
CT3I
INT
CTI0
CTI1
CTI2
CTI3
CT0
CT1
CT2
CT3
off 8-bit overflow interrupt fosc T2 RT2 T2ER External reset enable COMP S S S S S S TG TG STE R R R R R R T T RTE P4.0 P4.1 CMO (S) P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 S R T = = = set reset toggle toggle status T2 SFR address: TML2 TMH2 = = lower 8 bits higher 8 bits I/O port 4 CM1 (R) CM2 (T) INT COMP INT COMP INT 1/6 Prescaler T2 Counter 16-bit overflow interrupt
TG =
SU01447
Figure 13. Block Diagram of Timer 2 Capture Logic: The four 16-bit capture registers that Timer T2 is connected to are: CT0, CT1, CT2, and CT3. These registers are loaded with the contents of Timer T2, and an interrupt is requested upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These input signals are shared with port 1. The four interrupt flags are in the Timer T2 interrupt register (TM2IR special function register). If the capture facility is not required, these inputs can be regarded as additional external interrupt inputs. Using the capture control register CTCON (see Figure 14), these inputs may capture on a rising edge, a falling edge, or on either a rising or falling edge. The inputs are sampled during S1P1 of each cycle. When a selected edge is detected, the contents of Timer T2 are captured at the end of the cycle. Measuring Time Intervals Using Capture Registers: When a recurring external event is represented in the form of rising or falling edges on one of the four capture pins, the time between two events can be measured using Timer T2 and a capture register. When an event occurs, the contents of Timer T2 are copied into the relevant capture register and an interrupt request is generated. The interrupt service routine may then compute the interval time if it knows the previous contents of Timer T2 when the last event occurred. With a 12-MHz oscillator, Timer T2 can be programmed to overflow every 524 ms. When event interval times are shorter than this, computing the interval time is simple, and the interrupt service routine is short. For longer interval times, the Timer T2 extension routine may be used. Compare Logic: Each time Timer T2 is incremented, the contents of the three 16-bit compare registers CM0, CM1, and CM2 are compared with the new counter value of Timer T2. When a match is found, the corresponding interrupt flag in TM2IR is set at the end of the following cycle. When a match with CM0 occurs, the controller sets bits 0-5 of port 4 if the corresponding bits of the set enable register STE are at logic 1.
2003 Jan 28
18
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 CTCON (EBH) CTN3 (MSB) BIT CTCON.7 CTCON.6 CTCON.5 CTCON.4 CTCON.3 CTCON.2 CTCON.1 CTCON.0
6 CTP3
5 CTN2
4 CTP2
3 CTN1
2 CTP1
1 CTN1
0 CTP0 (LSB)
Reset Value = 00H
SYMBOL CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0
CAPTURE/INTERRUPT ON: Capture Register 3 triggered by a falling edge on CT3I Capture Register 3 triggered by a rising edge on CT3I Capture Register 2 triggered by a falling edge on CT2I Capture Register 2 triggered by a rising edge on CT2I Capture Register 1 triggered by a falling edge on CT1I Capture Register 1 triggered by a rising edge on CT1I Capture Register 0 triggered by a falling edge on CT0I Capture Register 0 triggered by a rising edge on CT0I
SU01085
Figure 14. Capture Control Register (CTCON) When a match with CM1 occurs, the controller resets bits 0-5 of port 4 if the corresponding bits of the reset/toggle enable register RTE are at logic 1 (see Figure 15 for RTE register function). If RTE is "0", then P4.n is not affected by a match between CM1 or CM2 and Timer 2. When a match with CM2 occurs, the controller "toggles" bits 6 and 7 of port 4 if the corresponding bits of the RTE are at logic 1. The port latches of bits 6 and 7 are not toggled. Two additional flip-flops store the last operation, and it is these flip-flops that are toggled. Thus, if the current operation is "set," the next operation will be "reset" even if the port latch is reset by software before the "reset" operation occurs. The first "toggle" after a chip RESET will set the port latch. The contents of these two flip-flops can be read at STE.6 and STE.7 (corresponding to P4.6 and P4.7, respectively). Bits STE.6 and STE.7 are read only (see Figure 16 for STE register function). A logic 1 indicates that the next toggle will set the port latch; a logic 0 indicates that the next toggle will reset the port latch. CM0, CM1, and CM2 are reset by the RST signal. The modified port latch information appears at the port pin during S5P1 of the cycle following the cycle in which a match occurred. If the port is modified by software, the outputs change during S1P1 of the following cycle. Each port 4 bit can be set or reset by software at any time. A hardware modification resulting from a comparator match takes precedence over a software modification in the same cycle. When the comparator results require a "set" and a "reset" at the same time, the port latch will be reset. Timer T2 Interrupt Flag Register TM2IR: Eight of the nine Timer T2 interrupt flags are located in special function register TM2IR (see Figure 17). The ninth flag is TM2CON.4. The CT0I and CT1I flags are set during S4 of the cycle in which the contents of Timer T2 are captured. CT0I is scanned by the interrupt logic during S2, and CT1I is scanned during S3. CT2I and CT3I are set during S6 and are scanned during S4 and S5. The associated interrupt requests are recognized during the following cycle. If these flags are polled, a transition at CT0I or CT1I will be recognized one cycle before a transition on CT2I or CT3I since registers are read during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the cycle following a match. CMI0 is scanned by the interrupt logic during S2; CMI1 and CMI2 are scanned during S3 and S4. A match will be recognized by the interrupt logic (or by polling the flags) two cycles after the match takes place. The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO) are set during S6 of the cycle in which the overflow occurs. These flags are recognized by the interrupt logic during the next cycle. Special function register IP1 (Figure 17) is used to determine the Timer T2 interrupt priority. Setting a bit high gives that function a high priority, and setting a bit low gives the function a low priority. The functions controlled by the various bits of the IP1 register are shown in Figure 17.
7 RTE (EFH) TP47 (MSB) BIT RTE.7 RTE.6 RTE.5 RTE.4 RTE.3 RTE.2 RTE.1 RTE.0
6 TP46
5 RP45
4 RP44
3 RP43
2 RP42
1 RO41
0 RP40 (LSB)
Reset Value = 00H
SYMBOL TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40
FUNCTION If "1" then P4.7 toggles on a match between CM1 and Timer T2 If "1" then P4.6 toggles on a match between CM1 and Timer T2 If "1" then P4.5 is reset on a match between CM1 and Timer T2 If "1" then P4.4 is reset on a match between CM1 and Timer T2 If "1" then P4.3 is reset on a match between CM1 and Timer T2 If "1" then P4.2 is reset on a match between CM1 and Timer T2 If "1" then P4.1 is reset on a match between CM1 and Timer T2 If "1" then P4.0 is reset on a match between CM1 and Timer T2
SU01086
Figure 15. Reset/Toggle Enable Register (RTE)
2003 Jan 28
19
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 STE (EEH) TG47 (MSB) BIT STE.7 STE.6 STE.5 STE.4 STE.3 STE.2 STE.1 STE.0
6 TG46
5 SP45
4 SP44
3 SP43
2 SP42
1 SP41
0 SP40 (LSB)
Reset Value = C0H
SYMBOL TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40
FUNCTION Toggle flip-flops Toggle flip-flops If "1" then P4.5 is set on a match between CM0 and Timer T2 If "1" then P4.4 is set on a match between CM0 and Timer T2 If "1" then P4.3 is set on a match between CM0 and Timer T2 If "1" then P4.2 is set on a match between CM0 and Timer T2 If "1" then P4.1 is set on a match between CM0 and Timer T2 If "1" then P4.0 is set on a match between CM0 and Timer T2
SU01087
Figure 16. Set Enable Register (STE) 7 TM2IR (C8H) T2OV (MSB) BIT TM2IR.7 TM2IR.6 TM2IR.5 TM2IR.4 TM2IR.3 TM2IR.2 TM2IR.1 TM2IR.0 SYMBOL T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0 FUNCTION Timer T2 16-bit overflow interrupt flag CM2 interrupt flag CM1 interrupt flag CM0 interrupt flag CT3 interrupt flag CT2 interrupt flag CT1 interrupt flag CT0 interrupt flag Interrupt Flag Register (TM2IR) 7 IP1 (F8H) PT2 (MSB) BIT IP1.7 IP1.6 IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 SYMBOL PT2 PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0 FUNCTION Timer T2 overflow interrupt(s) priority level Timer T2 comparator 2 interrupt priority level Timer T2 comparator 1 interrupt priority level Timer T2 comparator 0 interrupt priority level Timer T2 capture register 3 interrupt priority level Timer T2 capture register 2 interrupt priority level Timer T2 capture register 1 interrupt priority level Timer T2 capture register 0 interrupt priority level
SU01088
6 CMI2
5 CMI1
4 CMI0
3 CTI3
2 CTI2
1 CTI1
0 CTI0 (LSB)
Reset Value = 00H
6 PCM2
5 PCM1
4 PCM0
3 PCT3
2 PCT2
1 PCT1
0 PCT0 (LSB)
Reset Value = 00H
Timer 2 Interrupt Priority Register (IP1) Figure 17. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)
2003 Jan 28
20
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Timer T3, The Watchdog Timer In addition to Timer T2 and the standard timers, a watchdog timer is also incorporated on the 8xC554. The purpose of a watchdog timer is to reset the microcontroller if it enters erroneous processor states (possibly caused by electrical noise or RFI) within a reasonable period of time. An analogy is the "dead man's handle" in railway locomotives. When enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer within a specified length of time known as the "watchdog interval." Watchdog Circuit Description: The watchdog timer (Timer T3) consists of an 8-bit timer with an 11-bit prescaler as shown in Figure 18. The prescaler is fed with a signal whose frequency is 1/6 the oscillator frequency (0.5 MHz with a 12-MHz oscillator). The 8-bit timer is incremented every "t" seconds, where: t = 6 x 2048 x 1/fOSC (= 0.75 ms at fOSC = 16 MHz; = 0.5 ms at fOSC = 24 MHz) If the 8-bit timer overflows, a short internal reset pulse is generated which will reset the 8xC554. A short output reset pulse is also generated at the RST pin. This short output pulse (3 machine cycles) may be destroyed if the RST pin is connected to a capacitor. This would not, however, affect the internal reset operation. Watchdog operation is activated when external pin EW is tied low. When EW is tied low, it is impossible to disable the watchdog operation by software. How to Operate the Watchdog Timer: The watchdog timer has to be reloaded within periods that are shorter than the programmed watchdog interval; otherwise the watchdog timer will overflow and a system reset will be generated. The user program must therefore continually execute sections of code which reload the watchdog timer. The period of time elapsed between execution of these sections of code must never exceed the watchdog interval. When using a 16-MHz oscillator, the watchdog interval is programmable
between 0.75 ms and 196 ms. When using a 24-MHz oscillator, the watchdog interval is programmable between 0.5 ms and 127.5 ms. In order to prepare software for watchdog operation, a programmer should first determine how long his system can sustain an erroneous processor state. The result will be the maximum watchdog interval. As the maximum watchdog interval becomes shorter, it becomes more difficult for the programmer to ensure that the user program always reloads the watchdog timer within the watchdog interval, and thus it becomes more difficult to implement watchdog operation. The programmer must now partition the software in such a way that reloading of the watchdog is carried out in accordance with the above requirements. The programmer must determine the execution times of all software modules. The effect of possible conditional branches, subroutines, external and internal interrupts must all be taken into account. Since it may be very difficult to evaluate the execution times of some sections of code, the programmer should use worst case estimations. In any event, the programmer must make sure that the watchdog is not activated during normal operation. The watchdog timer is reloaded in two stages in order to prevent erroneous software from reloading the watchdog. First PCON.4 (WLE) must be set. The T3 may be loaded. When T3 is loaded, PCON.4 (WLE) is automatically reset. T3 cannot be loaded if PCON.4 (WLE) is reset. Reload code may be put in a subroutine as it is called frequently. Since Timer T3 is an up-counter, a reload value of 00H gives the maximum watchdog interval (255 ms with a 12-MHz oscillator), and a reload value of 0FFH gives the minimum watchdog interval (1 ms with a 12-MHz oscillator). In the idle mode, the watchdog circuitry remains active. When watchdog operation is implemented, the power-down mode cannot be used since both states are contradictory. Thus, when watchdog operation is enabled by tying external pin EW low, it is impossible to enter the power-down mode, and an attempt to set the power-down bit (PCON.1) will have no effect. PCON.1 will remain at logic 0.
INTERNAL BUS
VDD
fOSC/6
OVERFLOW PRESCALER (11-BIT) CLEAR TIMER T3 (8-BIT) LOAD LOADEN
P
RST INTERNAL RESET
WRITE T3 CLEAR WLE PCON.4 EW PD LOADEN PCON.1 RRST
INTERNAL BUS
SU00955
Figure 18. Watchdog Timer
2003 Jan 28
21
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
During the early stages of software development/debugging, the watchdog may be disabled by tying the EW pin high. At a later stage, EW may be tied low to complete the debugging process. Watchdog Software Example: The following example shows how watchdog operation might be handled in a user program. ;at the program start: T3 EQU 0FFH ;address of watchdog timer T3 PCON EQU 087H ;address of PCON SFR WATCH-INTV EQU 156 ;watchdog interval (e.g., 100 ms) ;to be inserted at each watchdog reload location within ;the user program: LCALL WATCHDOG ;watchdog service routine: WATCHDOG: ORL PCON,#10H ;set condition flag (PCON.4) MOV T3,WATCH-INV ;load T3 with watchdog interval RET If it is possible for this subroutine to be called in an erroneous state, then the condition flag WLE should be set at different parts of the main program. Serial I/O The 8xC554 is equipped with two independent serial ports: SIO0 and SIO1. SIO0 is a full duplex UART port and is similar to the Enhanced UART serial port. SIO1 accommodates the I2C bus. SIO0: SIO0 is a full duplex serial I/O port identical to that of the Enhanced UART except Time 2 cannot be used as a baud rate generator. Its operation is the same, including the use of timer 1 as a baud rate generator. Port 5 Operation Port 5 may be used to input up to 8 analog signals to the ADC. Unused ADC inputs may be used to input digital inputs. These inputs have an inherent hysteresis to prevent the input logic from drawing excessive current from the power lines when driven by analog signals. Channel to channel crosstalk (Ct) should be taken into consideration when both analog and digital signals are simultaneously input to Port 5 (see, D.C. characteristics in data sheet). Port 5 is not bidirectional and may not be configured as an output port. All six ports are multifunctional, and their alternate functions are listed in the Pin Descriptions section of this datasheet. Pulse Width Modulated Outputs The 8xC554 contains two pulse width modulated output channels (see Figure 19). These channels generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value, the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWMn. The PWM outputs may also be configured as a dual DAC. In this application, the PWM outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before they are integrated. The repetition frequency fPWM, at the PWMn outputs is give by: f PWM + f OSC (1 ) PWMP)
255
This gives a repetition frequency range of 246 Hz to 62.8 kHz (fOSC = 16 MHz). At fOSC = 24 MHz, the frequency range is 368 Hz to 83.4 Hz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven by push-pull drivers. These pins are not used for any other purpose. Prescaler frequency control register PWMP
PWMP (FEH) 7 MSB 6 5 4 3
Reset Value = 00H
2 1 0 LSB
PWMP.0-7
Prescaler division factor = PWMP + 1.
Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read. Reset Value = 00H
PWM0 (FCH) PWM1 (FDH) 7 MSB 6 5 4 3 2 1 0 LSB
PWM0/1.0-7} Low/high ratio of PWMn +
(PWMn) 255 * (PWMn)
Analog-to-Digital Converter The analog input circuitry consists of an 8-input analog multiplexer and a 10-bit, straight binary, successive approximation ADC. The A/D can also be operated in 8-bit mode with faster conversion times by setting bit ADC8 (AUXR1.7). The 8-bit results will be contained in the ADCH register. The analog reference voltage and analog power supplies are connected via separate input pins. For 10-bit accuracy, the conversion takes 50 machine cycles, i.e., 18.75 s at an oscillator frequency of 16 MHz, 12.5 s at an oscillator frequency of 24 MHz. For the 8-bit mode, the conversion takes 24 machine cycles. Input voltage swing is from 0 V to +5 V. Because the internal DAC employs a ratiometric potentiometer, there are no discontinuities in the converter characteristic. Figure 20 shows a functional diagram of the analog input circuitry. The ADC has the option of either being powered off in idle mode for reduced power consumption or being active in idle mode for reducing internal noise during the conversion. This option is selected by the AIDL bit of AUXR1 register (AUXR1.6). With the AIDL bit set, the ADC is active in the idle mode, and with the AIDL bit cleared, the ADC is powered off in idle mode.
2003 Jan 28
22
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
PWM0
8-BIT COMPARATOR INTERNAL BUS fOSC
OUTPUT BUFFER
PWM0
PRESCALER PWMP
8-BIT COUNTER
8-BIT COMPARATOR
OUTPUT BUFFER
PWM1
PWM1
SU01448
Figure 19. Functional Diagram of Pulse Width Modulated Outputs
STADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ANALOG INPUT MULTIPLEXER 10-BIT A/D CONVERTER ANALOG SUPPLY ANALOG GROUND + ANALOG REF. -
ADCON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
SU01467
Figure 20. Functional Diagram of Analog Input Circuitry 10-Bit Analog-to-Digital Conversion: Figure 21 shows the elements of a successive approximation (SA) ADC. The ADC contains a DAC which converts the contents of a successive approximation register to a voltage (VDAC) which is compared to the analog input voltage (Vin). The output of the comparator is fed to the successive approximation control logic which controls the successive approximation register. A conversion is initiated by setting ADCS in the ADCON register. ADCS can be set by software only or by either hardware or software. The software only start mode is selected when control bit ADCON.5 (ADEX) = 0. A conversion is then started by setting control bit ADCON.3 (ADCS). The hardware or software start mode is selected when ADCON.5 = 1, and a conversion may be started by setting ADCON.3 as above or by applying a rising edge to external pin STADC. When a conversion is started by applying a rising edge, a low level must be applied to STADC for at least one machine cycle followed by a high level for at least one machine cycle.
2003 Jan 28
23
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Vin VDAC
+ -
DAC
SUCCESSIVE APPROXIMATION REGISTER
SUCCESSIVE APPROXIMATION CONTROL LOGIC
START FULL SCALE 1 Vin 15/16 3/4 7/8 29/32
STOP 59/64
VDAC
1/2
0
1
2
3
4 t/tau
5
6
SU00958
Figure 21. Successive Approximation ADC The low-to-high transition of STADC is recognized at the end of a machine cycle, and the conversion commences at the beginning of the next cycle. When a conversion is initiated by software, the conversion starts at the beginning of the machine cycle which follows the instruction that sets ADCS. ADCS is actually implemented with two flip-flops: a command flip-flop which is affected by set operations, and a status flag which is accessed during read operations. The next two machine cycles are used to initiate the converter. At the end of the first cycle, the ADCS status flag is set and a value of "1" will be returned if the ADCS flag is read while the conversion is in progress. Sampling of the analog input commences at the end of the second cycle. During the next eight machine cycles, the voltage at the previously selected pin of port 5 is sampled, and this input voltage should be stable in order to obtain a useful sample. In any event, the input voltage slew rate must be less than 10 V/ms in order to prevent an undefined result. The successive approximation control logic first sets the most significant bit and clears all other bits in the successive approximation register (10 0000 0000B). The output of the DAC (50% full scale) is compared to the input voltage Vin. If the input voltage is greater than VDAC, then the bit remains set; otherwise it is cleared. The successive approximation control logic now sets the next most significant bit (11 0000 0000B or 01 0000 0000B, depending on the previous result), and VDAC is compared to Vin again. If the input voltage is greater than VDAC, then the bit being tested remains set; otherwise the bit being tested is cleared. This process is repeated until all ten bits have been tested, at which stage the result of the conversion is held in the successive approximation register. Figure 22 shows a conversion flow chart. The bit pointer identifies the bit under test. The conversion takes four machine cycles per bit. The end of the 10-bit conversion is flagged by control bit ADCON.4 (ADCI). The upper 8 bits of the result are held in special function register ADCH, and the two remaining bits are held in ADCON.7 (ADC.1) and ADCON.6 (ADC.0). The user may ignore the two least significant bits in ADCON and use the ADC as an 8-bit converter (8 upper bits in ADCH). In any event, the total actual conversion time is 50 machine cycles for the 8xC554. ADCI will be set and the ADCS status flag will be reset 50 cycles after the command flip-flop (ADCS) is set. Control bits ADCON.0, ADCON.1, and ADCON.2 are used to control an analog multiplexer which selects one of seven analog channels (see Figure 23). An ADC conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unaffected provided ADCI = logic 1; a new ADC conversion already in progress is aborted when the idle or power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode.
2003 Jan 28
24
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SOC
Start of Conversion
RESET SAR
[BIT POINTER] = MSB
[BIT]N = 1
CONVERSION TIME
1
TEST COMPLETE
0
[BIT]N = 0
[BIT POINTER] + 1
TEST BIT POINTER END
END
EOC END OF CONVERSION
SU00959
Figure 22. A/D Conversion Flowchart
2003 Jan 28
25
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 ADCON (C5H) Bit ADCON.7 ADCON.6 ADCON.5 Symbol ADC.1 ADC.0 ADEX ADC.1
(MSB)
6
5
4
3
2
1
0 AADR0
(LSB)
Reset Value = xx00 0000B
ADC.0 ADEX
ADCI ADCS AADR2 AADR1
Function Bit 1 of ADC result Bit 0 of ADC result Enable external start of conversion by STADC 0 = Conversion can be started by software only (by setting ADCS) 1 = Conversion can be started by software or externally (by a rising edge on STADC) ADC interrupt flag: this flag is set when an A/D conversion result is ready to be read. An interrupt is invoked if it is enabled. The flag may be cleared by the interrupt service routine. While this flag is set, the ADC cannot start a new conversion. ADCI cannot be set by software. ADC start and status: setting this bit starts an A/D conversion. It may be set by software or by the external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset immediately after the interrupt flag has been set. ADCS cannot be reset by software. A new conversion may not be started while either ADCS or ADCI is high. ADCI 0 0 1 1 ADCS 0 1 0 1 ADC Status ADC not busy; a conversion can be started ADC busy; start of a new conversion is blocked Conversion completed; start of a new conversion requires ADCI=0 Conversion completed; start of a new conversion requires ADCI=0
ADCON.4
ADCI
ADCON.3
ADCS
If ADCI is cleared by software while ADCS is set at the same time, a new A/D conversion with the same channel number may be started. But it is recommended to reset ADCI before ADCS is set. ADCON.2 ADCON.1 ADCON.0 AADR2 AADR1 AADR0 Analogue input select: this binary coded address selects one of the eight analogue port bits of P5 to be input to the converter. It can only be changed when ADCI and ADCS are both LOW. AADR2 0 0 0 0 1 1 1 AADR1 0 0 1 1 0 0 1 AADR0 0 1 0 1 0 1 0 Selected Analog Channel ADC0 (P5.0) ADC1 (P5.1) ADC2 (P5.2) ADC3 (P5.3) ADC4 (P5.4) ADC5 (P5.5) ADC6 (P5.6)
SU01468
Figure 23. ADC Control Register (ADCON)
2003 Jan 28
26
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
10-Bit ADC Resolution and Analog Supply: Figure 24 shows how the ADC is realized. The ADC has its own supply pins (AVDD and AVSS) and two pins (Vref+ and Vref-) connected to each end of the DAC's resistance-ladder. The ladder has 1023 equally spaced taps, separated by a resistance of "R". The first tap is located 0.5 x R above Vref-, and the last tap is located 1.5 x R below Vref+. This gives a total ladder resistance of 1024 x R. This structure ensures that the DAC is monotonic and results in a symmetrical quantization error as shown in Figure 26. For input voltages between Vref- and (Vref-) + 1/2 LSB, the 10-bit result of an A/D conversion will be 00 0000 0000B = 000H. For input voltages between (Vref+) - 3/2 LSB and Vref+, the result of a conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref- may be between AVDD + 0.2 V and AVSS - 0.2 V. AVref+ should be positive with respect to AVref-, and the input voltage (Vin) should be between AVref+ and AVref-. If the analog input voltage range is from 2 V to 4 V, then 10-bit resolution can be obtained over this range if AVref+ = 4 V and AVref- = 2 V. The result can always be calculated from the following formula: Result + 1024 V IN * AV ref* AV ref) * AV ref*
Power Reduction Modes The 8xC554 has two reduced power modes of operation: the idle mode and the power-down mode. These modes are entered by setting bits in the PCON special function register. When the 8xC554 enters the idle mode, the following functions are disabled: CPU Timer T2 PWM0, PWM1 ADC (halted) (halted and reset) (reset; outputs are high) (may be enabled for operation in Idle mode by setting bit AIDC (AUXR1.6) ).
In idle mode, the following functions remain active: Timer 0 Timer 1 Timer T3 SIO0 SIO1 External interrupts When the 8xC554 enters the power-down mode, the oscillator is stopped. The power-down mode is entered by setting the PD bit in the PCON register. The PD bit can only be set if the EW input is tied HIGH.
AVref+ R/2 1023 R R 1022 R START MSB
1021 SUCCESSIVE APPROXIMATION REGISTER SUCCESSIVE APPROXIMATION CONTROL LOGIC
TOTAL RESISTANCE = 1023R + 2 x R/ = 1024R
DECODER
3
2 READY R R R/2 1 0 LSB
AVref-
Vref
- COMPARATOR
Vin Value 0000 0000 00 Value 1111 1111 11
+ is output for voltages Vref- to (Vref- + 1/2 LSB) is output for voltages (Vref+ - 3/2 LSB) to Vref+
SU00961
Figure 24. ADC Realization
2003 Jan 28
27
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SmN+1 IN+1 SmN
RmN+1
IN
+
RmN
TO COMPARATOR
MULTIPLEXER
RS VANALOG
INPUT
CS
CC
Rm = 0.5 - 3 k CS + CC = 15 pF maximum RS = Recommended < 9.6 k for 1 LSB @ 12 MHz NOTE: Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion is initiated, switch Sm closes for 8tCY (4 s @ 12 MHz crystal frequency) during which time capacitance CS + CC is charged. It should be noted that the sampling causes the analog input to present a varying load to an analog source.
SU01449
Figure 25. A/D Input: Equivalent Circuit
CODE OUT
101
100
011
010
001
000 0 q 2q 3q 4q 5q Vin QUANTIZATION ERROR q = LSB = 5 mV Vin - Vdigital
+ q/2
- q/2 SYMMETRICAL QUANTIZATION ERROR
Vin
SU00963
Figure 26. Effective Conversion Characteristic
2003 Jan 28
28
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Interrupts The 8xC554 has fifteen interrupt sources, each of which can be assigned one of four priority levels. The five interrupt sources common to the 80C51 are the external interrupts (INT0 and INT1), the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O interrupt (RI or TI). In the 8xC554, the standard serial interrupt is called SIO0. The eight Timer T2 interrupts are generated by flags CTI0-CT13, CMI0-CMI2, and by the logical OR of flags T2OV and T2BO. Flags CTI0 to CT13 are set by input signals CT0I to CT3i. Flags CMI0 to CMI2 are set when a match occurs between Timer T2 and the compare registers CM0, CM1, and CM2. When an 8-bit or 16-bit overflow occurs, flags T2BO and T2OV are set, respectively. These nine flags are not cleared by hardware and must be reset by software to avoid recurring interrupts. The ADC interrupt is generated by the ADCI flag in the ADC control register (ADCON). This flag is set when an ADC conversion result is ready to be read. ADCI is not cleared by hardware and must be reset by software to avoid recurring interrupts. The SIO1 (I2C) interrupt is generated by the SI flag in the SIO1 control register (S1CON). This flag is set when S1STA is loaded with a valid status code. The ADCI flag may be reset by software. It cannot be set by software. All other flags that generate interrupts may be set or cleared by software, and the effect is the same as setting or resetting the flags by hardware. Thus, interrupts may be generated by software and pending interrupts can be canceled by software. Interrupt Enable Registers: Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the
interrupt enable special function registers IEN0 and IEN1. All interrupt sources can also be globally enabled or disabled by setting or clearing bit EA in IEN0. The interrupt enable registers are described in Figures 27 and 28. There are 3 SFRs associated with each of the four-level interrupts. They are the IENx, IPx, and IPxH. (See Figures 29, 30, and 31.) The IPxH (Interrupt Priority High) register makes the four-level interrupt structure possible. The function of the IPxH SFR is simple and when combined with the IPx SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table: PRIORITY BITS IPxH.x 0 0 1 1 IPx.x 0 1 0 1 INTERRUPT PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
7 IEN0 (A8H) EA (MSB) BIT IEN0.7
6 EAD
5 ES1
4 ES0
3 ET1
2 EX1
1 ET0
0 EX0 (LSB)
SYMBOL EA
FUNCTION Global enable/disable control 0 = No interrupt is enabled 1 = Any individually enabled interrupt will be accepted Eanble ADC interrupt Enable SIO1 (I2C) interrupt Enable SIO0 (UART) interrupt Enable Timer 1 interrupt Enable External interrupt 1 Enable Timer 0 interrupt Enable External interrupt 0
IEN0.6 IEN0.5 IEN0.4 IEN0.3 IEN0.2 IEN0.1 IEN0.0
EAD ES1 ES0 ET1 EX1 ET0 EX0
SU00762
Figure 27. Interrupt Enable Register (IEN0)
2003 Jan 28
29
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 IEN1 (E8H) ET2 (MSB) BIT IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0
6 ECM2
5 ECM1
4 ECM0
3 ECT3
2 ECT2
1 ECT1
0 ECT0 (LSB)
SYMBOL ET2 ECM2 ECM1 ECM0 ECT3 ECT2 ECT1 ECT0
FUNCTION Enable Timer T2 overflow interrupt(s) Enable T2 Comparator 2 interrupt Enable T2 Comparator 1 interrupt Enable T2 Comparator 0 interrupt Enable T2 Capture register 3 interrupt Enable T2 Capture register 2 interrupt Enable T2 Capture register 1 interrupt Enable T2 Capture register 0 interrupt
SU00755
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled. Figure 28. Interrupt Enable Register (IEN1)
7 IP0 (B8H) - (MSB) BIT IP0.7 IP0.6 IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
6 PAD
5 PS1
4 PS0
3 PT1
2 PX1
1 PT0
0 PX0 (LSB)
SYMBOL - PAD PS1 PS0 PT1 PX1 PT0 PX0
FUNCTION Unused ADC interrupt priority level SIO1 (I2C) interrupt priority level SIO0 (UART) interrupt priority level Timer 1 interrupt priority level External interrupt 1 priority level Timer 0 interrupt priority level External interrupt 0 priority level
SU00763
Figure 29. Interrupt Priority Register (IP0)
7 IP0H (B7H) - (MSB) BIT IP0H.7 IP0H.6 IP0H.5 IP0H.4 IP0H.3 IP0H.2 IP0H.1 IP0H.0
6 PADH
5 PS1H
4 PS0H
3 PT1H
2 PX1H
1 PT0H
0 PX0H (LSB)
SYMBOL - PADH PS1H PS0H PT1H PX1H PT0H PX0H
FUNCTION Unused ADC interrupt priority level high SIO1 (I2C) interrupt priority level high SIO0 (UART) interrupt priority level high Timer 1 interrupt priority level high External interrupt 1 priority level high Timer 0 interrupt priority level high External interrupt 0 priority level high
SU00983
Figure 30. Interrupt Priority Register High (IP0H)
2003 Jan 28
30
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
7 IP1 (F8H) PT2 (MSB) BIT IP1.7 IP1.6 IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0
6 PCM2
5 PCM1
4 PCM0
3 PCT3
2 PCT2
1 PCT1
0 PCT0 (LSB)
SYMBOL PT2 PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0
FUNCTION T2 overflow interrupt(s) priority level T2 comparator 2 interrupt priority level T2 comparator 1 interrupt priority level T2 comparator 0 interrupt priority level T2 capture register 3 interrupt priority level T2 capture register 2 interrupt priority level T2 capture register 1 interrupt priority level T2 capture register 0 interrupt priority level
SU00764
Figure 31. Interrupt Priority Register (IP1)
7 IP1H (F7H) PT2H (MSB) BIT IP1H.7 IP1H.6 IP1H.5 IP1H.4 IP1H.3 IP1H.2 IP1H.1 IP1H.0
6
5
4
3
2 PCT2H
1 PCT1H
0 PCT0H (LSB)
PCM2H PCM1H PCM0H PCT3H
SYMBOL PT2H PCM2H PCM1H PCM0H PCT3H PCT2H PCT1H PCT0H
FUNCTION T2 overflow interrupt(s) priority level high T2 comparator 2 interrupt priority level high T2 comparator 1 interrupt priority level high T2 comparator 0 interrupt priority level high T2 capture register 3 interrupt priority level high T2 capture register 2 interrupt priority level high T2 capture register 1 interrupt priority level high T2 capture register 0 interrupt priority level high
SU00984
Figure 32. Interrupt Priority Register High (IP1H)
Table 3.
Interrupt Priority Structure
NAME X0 S1 ADC T0 CT0 CM0 X1 CT1 CM1 T1 CT2 CM2 S0 CT3 T2 PRIORITY WITHIN LEVEL (highest)
Table 4.
Interrupt Vector Addresses
NAME X0 T0 X1 T1 S0 S1 CT0 CT1 CT2 CT3 ADC CM0 CM1 CM2 T2 VECTOR ADDRESS 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H
SOURCE External interrupt 0 SIO1 (I2C) ADC completion Timer 0 overflow T2 capture 0 T2 compare 0 External interrupt 1 T2 capture 1 T2 compare 1 Timer 1 overflow T2 capture 2 T2 compare 2 SIO0 (UART) T2 capture 3 Timer T2 overflow
SOURCE External interrupt 0 Timer 0 overflow External interrupt 1 Timer 1 overflow SIO0 (UART) SIO1 (I2C) T2 capture 0 T2 capture 1 T2 capture 2 T2 capture 3 ADC completion T2 compare 0 T2 compare 1 T2 compare 2 T2 overflow
(lowest)
2003 Jan 28
31
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SIO1, I2C Serial I/O: The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are: - Bidirectional data transfer between masters and slaves - Multimaster bus (no central master) - Arbitration between simultaneously transmitting masters without corruption of serial data on the bus - Serial clock synchronization allows devices with different bit rates to communicate via one serial bus - Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer - The I2C bus may be used for test and diagnostic purposes The output latches of P1.6 and P1.7 must be set to logic 1 in order to enable SIO1. The 8xC554 on-chip I2C logic provides a serial interface that meets the I2C bus specification and supports all transfer modes (other than the low-speed mode) from and to the I2C bus. The SIO1 logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (S1STA) reflects the status of SIO1 and the I2C bus. The CPU interfaces to the I2C logic via the following four special function registers: S1CON (SIO1 control register), S1STA (SIO1 status register), S1DAT (SIO1 data register), and S1ADR (SIO1 slave address register). The SIO1 logic interfaces to the external I2C bus via two port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial data line). A typical I2C bus configuration is shown in Figure 33, and Figure 34 shows how a data transfer is accomplished on the bus. Depending on the state of the direction bit (R/W), two types of data transfers are possible on the I2C bus: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released.
Modes of Operation: The on-chip SIO1 logic may operate in the following four modes: 1. Master Transmitter Mode: Serial data output through P1.7/SDA while P1.6/SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and we say that a "W" is transmitted. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. 2. Master Receiver Mode: The first byte transmitted contains the slave address of the transmitting device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 1, and we say that an "R" is transmitted. Thus the first byte transmitted is SLA+R. Serial data is received via P1.7/SDA while P1.6/SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer. 3. Slave Receiver Mode: Serial data and the serial clock are received through P1.7/SDA and P1.6/SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. 4. Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.7/SDA while the serial clock is input through P1.6/SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, SIO1 may operate as a master and as a slave. In the slave mode, the SIO1 hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, SIO1 switches to the slave mode immediately and can detect its own slave address in the same serial transfer.
2003 Jan 28
32
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
VDD RP RP SDA I2C bus SCL
P1.7/SDA
P1.6/SCL OTHER DEVICE WITH I2C INTERFACE OTHER DEVICE WITH I2C INTERFACE
8XC554
SU00964
Figure 33. Typical I2C Bus Configuration
SDA
STOP CONDITION REPEATED START CONDITION SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGMENT SIGNAL FROM RECEIVER
MSB
ACKNOWLEDGMENT SIGNAL FROM RECEIVER
CLOCK LINE HELD LOW WHILE INTERRUPTS ARE SERVICED
SCL S START CONDITION
1
2
7
8
9 ACK
1
2
3-8
9 ACK
P/S
REPEATED IF MORE BYTES ARE TRANSFERRED
SU00965
Figure 34. Data Transfer on the SIO1 Implementation and Operation: Figure 35 shows how the on-chip I2C bus interface is implemented, and the following text describes the individual blocks. INPUT FILTERS AND OUTPUT STAGES The input filters have I2C compatible input levels. If the input voltage is less than 1.5 V, the input logic level is interpreted as 0; if the input voltage is greater than 3.0 V, the input logic level is interpreted as 1. Input signals are synchronized with the internal clock (fOSC/2), and spikes shorter than three oscillator periods are filtered out. The output stages consist of open drain transistors that can sink 3 mA at VOUT < 0.4 V. These open drain outputs do not have clamping diodes to VDD. Thus, if the device is connected to the I2C bus and VDD is switched off, the I2C bus is not affected. ADDRESS REGISTER, S1ADR This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (00H) recognition.
I2 C
Bus
COMPARATOR The comparator compares the received 7-bit slave address with its own slave address (7 most significant bits in S1ADR). It also compares the first received 8-bit byte with the general call address (00H). If an equality is found, the appropriate status bits are set and an interrupt is requested. SHIFT REGISTER, S1DAT This 8-bit special function register contains a byte of serial data to be transmitted or a byte which has just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT.
2003 Jan 28
33
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
8
S1ADR
ADDRESS REGISTER
P1.7
COMPARATOR INPUT FILTER
P1.7/SDA OUTPUT STAGE S1DAT SHIFT REGISTER ACK
8
INPUT FILTER
ARBITRATION & SYNC LOGIC
P1.6/SCL OUTPUT STAGE TIMER 1 OVERFLOW S1CON P1.6 SERIAL CLOCK GENERATOR
TIMING & CONTROL LOGIC
fOSC/4
INTERRUPT
CONTROL REGISTER
8
STATUS BITS
STATUS DECODER
S1STA
STATUS REGISTER 8
su00966
Figure 35.
I 2C
Bus Serial Interface Block Diagram
2003 Jan 28
34
INTERNAL BUS
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
ARBITRATION AND SYNCHRONIZATION LOGIC In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and SIO1 immediately changes from master transmitter to slave receiver. SIO1 will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while SIO1 is returning a "not acknowledge: (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, SIO1 generates no further clock pulses. Figure 36 shows the arbitration procedure.
The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the "mark" duration is determined by the device that generates the shortest "marks," and the "space" duration is determined by the device that generates the longest "spaces." Figure 37 shows the synchronization procedure. A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared.
(3) (1) (1) (2)
SDA
SCL
1
2
3
4
8
9 ACK
1. Another device transmits identical serial data. 2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is lost, and SIO1 enters the slave receiver mode. 3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.
SU00967
Figure 36. Arbitration Procedure
SDA
(1)
(3)
(1)
SCL
(2)
MARK DURATION
SPACE DURATION
1. Another service pulls the SCL line low before the SIO1 "mark" duration is complete. The serial clock generator is immediately reset and commences with the "space" duration by pulling SCL low. 2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state until the SCL line is released. 3. The SCL line is released, and the serial clock generator commences with the mark duration.
SU00968
Figure 37. Serial Clock Synchronization
2003 Jan 28
35
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SERIAL CLOCK GENERATOR This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the master transmitter or master receiver mode. It is switched off when SIO1 is in a slave mode. The programmable output clock frequencies are: fOSC/60, fOSC/4800, and the Timer 1 overflow rate divided by eight. The output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other SCL clock sources as described above. TIMING AND CONTROL The timing and control logic generates the timing and control signals for serial byte handling. This logic block provides the shift pulses for S1DAT, enables the comparator, generates and detects start and stop conditions, receives and transmits acknowledge bits, controls the master and slave modes, contains interrupt request logic, and monitors the I2C bus status. CONTROL REGISTER, S1CON This 7-bit special function register is used by the microcontroller to control the following SIO1 functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. STATUS DECODER AND STATUS REGISTER The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the status register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code is sufficient for most of the service routines (see the software example in this section). The Four SIO1 Special Function Registers: The microcontroller interfaces to SIO1 via four special function registers. These four SFRs (S1ADR, S1DAT, S1CON, and S1STA) are described individually in the following sections. The Address Register, S1ADR: The CPU can read from and write to this 8-bit, directly addressable SFR. S1ADR is not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a master mode. In the slave modes, the seven most significant bits must be loaded with the microcontroller's own slave address, and, if the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored.
7 S1ADR (DBH) X 6 X 5 X 4 X 3 X 2 X 1 X 0 GC
read from and write to this 8-bit, directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag is set. Data in S1DAT remains stable as long as SI is set. Data in S1DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT.
7 S1DAT (DAH) SD7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0
shift direction
SD7 - SD0: Eight bits to be transmitted or just received. A logic 1 in S1DAT corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. Serial data shifts through S1DAT from right to left. Figure 38 shows how data in S1DAT is serially transferred to and from the SDA line. S1DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT via a buffer (BSD7) on the falling edges of clock pulses on the SCL line. When the CPU writes to S1DAT, BSD7 is loaded with the content of S1DAT.7, which is the first bit to be transmitted to the SDA line (see Figure 39). After nine serial clock pulses, the eight bits in S1DAT will have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the eight transmitted bits are shifted back into S1DAT. The Control Register, S1CON: The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENS1 = "0".
7 S1CON (D8H) CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0
own slave address
ENS1, THE SIO1 ENABLE BIT ENS1 = "0": When ENS1 is "0", the SDA and SCL outputs are in a high impedance state. SDA and SCL input signals are ignored, SIO1 is in the "not addressed" slave state, and the STO bit in S1CON is forced to "0". No other bits are affected. P1.6 and P1.7 may be used as open drain I/O ports. ENS1 = "1": When ENS1 is "1", SIO1 is enabled. The P1.6 and P1.7 port latches must be set to logic 1. ENS1 should not be used to temporarily release SIO1 from the I2C bus since, when ENS1 is reset, the I2C bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text).
The most significant bit corresponds to the first bit received from the I2C bus after a start condition. A logic 1 in S1ADR corresponds to a high level on the I2C bus, and a logic 0 corresponds to a low level on the bus. The Data Register, S1DAT: S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can
2003 Jan 28
36
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
INTERNAL BUS
SDA
8
BSD7
S1DAT
ACK
SCL SHIFT PULSES
SU00969
Figure 38. Serial Input/Output Configuration
SDA
D7
D6
D5
D4
D3
D2
D1
D0
A
SCL
SHIFT ACK & S1DAT SHIFT IN
ACK
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
A
S1DAT
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
SHIFT BSD7 SHIFT OUT
BSD7
D7
D6
D5
D4
D3
D2
D1
D0
(3)
LOADED BY THE CPU (1) Valid data in S1DAT (2) Shifting data in S1DAT and ACK (3) High level on SDA
SU00970
Figure 39. Shift-in and Shift-out Timing In the following text, it is assumed that ENS1 = "1". STA, THE START FLAG STA = "1": When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator. If STA is set while SIO1 is already in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. STA = "0": When the STA bit is reset, no START condition or repeated START condition will be generated. STO, THE STOP FLAG STO = "1": When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined "not addressed" slave receiver mode. The STO flag is automatically cleared by hardware.
2003 Jan 28
37
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
If the STA and STO bits are both set, the a STOP condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition. STO = "0": When the STO bit is reset, no STOP condition will be generated. SI, THE SERIAL INTERRUPT FLAG SI = "1": When the SI flag is set, then, if the EA and ES1 (interrupt enable register) bits are also set, a serial interrupt is requested. SI is set by hardware when one of 25 of the 26 possible SIO1 states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. SI = "0": When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. AA, THE ASSERT ACKNOWLEDGE FLAG AA = "1": If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: - The "own slave address" has been received - The general call address has been received while the general call bit (GC) in S1ADR is set - A data byte has been received while SIO1 is in the master receiver mode - A data byte has been received while SIO1 is in the addressed slave receiver mode AA = "0": if the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on SCL when: - A data has been received while SIO1 is in the master receiver mode - A data byte has been received while SIO1 is in the addressed slave receiver mode
When SIO1 is in the addressed slave transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 43). When SI is cleared, SIO1 leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition. When SIO1 is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO1 can be temporarily released from the I2C bus while the bus status is monitored. While SIO1 is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. CR0, CR1, AND CR2, THE CLOCK RATE BITS These three bits determine the serial clock frequency when SIO1 is in a master mode. The various serial rates are shown in Table 5. A 12.5 kHz bit rate may be used by devices that interface to the I2C bus via standard I/O port lines which are software driven and slow. 100 kHz is usually the maximum bit rate and can be derived from a 8 MHz, 6 MHz, or a 3-MHz oscillator. A variable bit rate (0.24 kHz to 62.5 kHz) may also be used if Timer 1 is not required for any other purpose while SIO1 is in a master mode. The frequencies shown in Table 5 are unimportant when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 100 kHz. The Status Register, S1STA: S1STA is an 8-bit read-only special function register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial interrupt is requested. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = "1"). A valid status code is present in S1STA one machine cycle after SI is set by hardware and is still present one machine cycle after SI has been reset by software.
Table 5.
CR2 0 0 0 0 1 1 1 1
Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 3 MHz 23 27 31 37 6.25 50 100 0.24 < 62.5 0 < 255 6 MHz 47 54 63 75 12.5 100 200 0.49 < 62.5 0 < 254 8 MHz 62.5 71 83.3 100 17 1331 2671 0.65 < 55.6 0 < 253 12 MHz2 94 1071 1251 1501 25 2001 4001 0.98 < 50.0 0 < 251 15 MHz2 1171 1341 1561 1881 31 2501 5001 1.22 < 52.1 0 < 250 fOSC DIVIDED BY 128 112 96 80 48 60 30 48 x (256 - (reload value Timer 1)) Reload value Timer 1 in Mode 2.
NOTES: 1. These frequencies exceed the upper limit of 100 kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 2. At fOSC = 12 MHz/15 MHz the maximum I2C bus rate of 100 kHz cannot be realized due to the fixed divider rates.
2003 Jan 28
38
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
More Information on SIO1 Operating Modes: The four operating modes are: - Master Transmitter - Master Receiver - Slave Receiver - Slave Transmitter Data transfers in each mode of operation are shown in Figures 40-43. These figures contain the following abbreviations: Abbreviation S SLA R W A A Data P Explanation Start condition 7-bit slave address Read bit (high level at SDA) Write bit (low level at SDA) Acknowledge bit (low level at SDA) Not acknowledge bit (high level at SDA) 8-bit data byte Stop condition
may switch to the master receiver mode by loading S1DAT with SLA+R). Master Receiver Mode: In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 41). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load S1DAT with the 7-bit slave address and the data direction bit (SLA+R). The SI bit in S1CON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. These are 40H, 48H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 7. ENS1, CR1, and CR0 are not affected by the serial transfer and are not referred to in Table 7. After a repeated start condition (state 10H), SIO1 may switch to the master transmitter mode by loading S1DAT with SLA+W. Slave Receiver Mode: In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 42). To initiate the slave receiver mode, S1ADR and S1CON must be loaded as follows:
7 S1ADR (DBH) X 6 X 5 X 4 X 3 X 2 X 1 X 0 GC
In Figures 40-43, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the S1STA register. At these points, a service routine must be executed to continue or complete the serial transfer. These service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. When a serial interrupt routine is entered, the status code in S1STA is used to branch to the appropriate service routine. For each status code, the required software action and details of the following serial transfer are given in Tables 6-10. Master Transmitter Mode: In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 40). Before the master transmitter mode can be entered, S1CON must be initialized as follows:
7 S1CON (D8H) CR2 bit rate 6 ENS1 1 5 STA 0 4 STO 0 3 SI 0 2 AA X 1 CR1 0 CR0
own slave address
The upper 7 bits are the address to which SIO1 will respond when addressed by a master. If the LSB (GC) is set, SIO1 will respond to the general call address (00H); otherwise it ignores the general call address.
7 S1CON (D8H) CR2 X 6 ENS1 1 5 STA 0 4 STO 0 3 SI 0 2 AA 1 1 CR1 X 0 CR0 X
bit rate
CR0, CR1, and CR2 define the serial bit rate. ENS1 must be set to logic 1 to enable SIO1. If the AA bit is reset, SIO1 will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. In other words, if AA is reset, SIO0 cannot enter a slave mode. STA, STO, and SI must be reset. The master transmitter mode may now be entered by setting the STA bit using the SETB instruction. The SIO1 logic will now test the I2C bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the status register (S1STA) will be 08H. This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit (SLA+W). The SI bit in S1CON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. There are 18H, 20H, or 38H for the master mode and also 68H, 78H, or B0H if the slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 6. After a repeated start condition (state 10H). SIO1
CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1 must be set to logic 1 to enable SIO1. The AA bit must be set to enable SIO1 to acknowledge its own slave address or the general call address. STA, STO, and SI must be reset. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be "0" (W) for SIO1 to operate in the slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (I) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 8. The slave receiver mode may also be entered if arbitration is lost while SIO1 is in the master mode (see status 68H and 78H). If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus.
2003 Jan 28
39
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
MT
SUCCESSFUL TRANSMISSION TO A SLAVE RECEIVER
NEXT TRANSFER STARTED WITH A REPEATED START CONDITION
NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS
NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE
ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE
ARBITRATION LOST AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Data
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 6.
Figure 40. Format and States in the Master Transmitter Mode
2003 Jan 28
CCC CCC CCC CCC CCC CCC CCC CCCCCCC CCCCCCC CCCCCCC CCC CCCCC CCCCCCCC C CCC CCCCC CCCCCCCC C
S SLA W A DATA A P 08H 18H 28H S SLA W 10H A P R 20H A P 30H A or A OTHER MST CONTINUES A or A OTHER MST CONTINUES 38H 38H A OTHER MST CONTINUES 68H 78H 80H TO CORRESPONDING STATES IN SLAVE MODE
TO MST/REC MODE ENTRY = MR
CCCC C CC C CCCC CCCC CCC CCCC CCCC CCCC
SU00971
40
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
MR
SUCCESSFUL RECEPTION FROM A SLAVE TRANSMITTER
NEXT TRANSFER STARTED WITH A REPEATED START CONDITION
NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS
ARBITRATION LOST IN SLAVE ADDRESS OR ACKNOWLEDGE BIT
ARBITRATION LOST AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
DATA
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 7.
2003 Jan 28
CCC CCC CCC CCC CCCCCCC CCCCCCC CCCCCCC CCCCCCCCCC CC C CCCCCCCC CCCCCCCCCC CC C CCCCCCCC
S SLA R A DATA A DATA A P 08H 40H 50H 58H S SLA R 10H A P W 48H TO MST/TRX MODE ENTRY = MT A or A OTHER MST CONTINUES 38H A OTHER MST CONTINUES 68H 78H 80H TO CORRESPONDING STATES IN SLAVE MODE
Figure 41. Format and States in the Master Receiver Mode
41
CCC CCC CCC
A 38H
OTHER MST CONTINUES
CC CCCC CCCCC C CCCC CCCC CCCC
SU00972
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
RECEPTION OF THE OWN SLAVE ADDRESS AND ONE OR MORE DATA BYTES ALL ARE ACKNOWLEDGED.
LAST DATA BYTE RECEIVED IS NOT ACKNOWLEDGED
ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE
RECEPTION OF THE GENERAL CALL ADDRESS AND ONE OR MORE DATA BYTES
LAST DATA BYTE IS NOT ACKNOWLEDGED
ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE BY GENERAL CALL
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Data
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 8.
Figure 42. Format and States in the Slave Receiver Mode
2003 Jan 28
CCC CCC CCC CCC CCC CCCCCC CCCCCCC C CCC CCC CCCCCC CCCCCCC C
S SLA W A DATA A DATA SLA A P or S 60H 80H 80H A0H A P or S 88H A 68H
CCC CCC CCC CCC CCC CCCCCC CCCCC C CCC CCC CCCCCC CCCCC C CCC CCC CCCCCC CCCCC C
GENERAL CALL A DATA A DATA A P or S 70H 90H 90H A0H A P or S 98H A 78H
CC C CCCC C CCCC CCCC CCC CCCC CCCC CCCC
SU00973
42
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
RECEPTION OF THE OWN SLAVE ADDRESS AND TRANSMISSION OF ONE OR MORE DATA BYTES
S
SLA
R
A
DATA
A8H
A
ARBITRATION LOST AS MST AND ADDRESSED AS SLAVE
FROM MASTER TO SLAVE
B0H
LAST DATA BYTE TRANSMITTED. SWITCHED TO NOT ADDRESSED SLAVE (AA BIT IN S1CON = "0"
A
All "1"s
FROM SLAVE TO MASTER
C8H
DATA
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
n
THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I2C BUS. SEE TABLE 9.
Figure 43. Format and States of the Slave Transmitter Mode
2003 Jan 28
43
CCC CCC CCC
CCCCCCCCCC CC C CCC C C C CCCCCCCCCC CCCCCCCC CC
A DATA A P or S B8H C0H
CCC CCC CCC
CCCCCCCC CCCCCCCC CCCCCCCC
CC CC CCCC CCCC CCCC CCCC
P or S
SU00974
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 6.
STATUS CODE (S1STA) 08H 10H
Master Transmitter Mode
STATUS OF THE I2C BUS AND SIO1 HARDWARE A START condition has been transmitted A repeated START condition h b diti has been transmitted SLA+W has been transmitted; ACK has been received b id APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA Load SLA+W Load SLA+W or Load SLA+R Load data byte or no S1DAT action or no S1DAT action or no S1DAT action X X X 0 1 0 1 TO S1CON STO 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 AA X X X X X X X SLA+W will be transmitted; ACK bit will be received As above SLA+W will be transmitted; SIO1 will be switched to MST/REC mode Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted; STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset I2C bus will be released; not addressed slave will be entered A START condition will be transmitted when the bus becomes free NEXT ACTION TAKEN BY SIO1 HARDWARE
18H
20H
SLA+W has been transmitted; NOT ACK hb id has been received
Load data byte or no S1DAT action or no S1DAT action or no S1DAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
28H
Data byte in S1DAT has been transmitted; ACK hb id has been received
Load data byte or no S1DAT action or no S1DAT action or no S1DAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
30H
Data byte in S1DAT has been transmitted; NOT ACK h b id has been received
Load data byte or no S1DAT action or no S1DAT action or no S1DAT action
0 1 0 1
0 0 1 1
0 0 0 0
X X X X
38H
Arbitration lost in SLA+R/W or Data b D bytes
No S1DAT action or No S1DAT action
0 1
0 0
0 0
X X
2003 Jan 28
44
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 7.
STATUS CODE (S1STA) 08H 10H
Master Receiver Mode
STATUS OF THE I2C BUS AND SIO1 HARDWARE A START condition has been transmitted A repeated START condition h b diti has been transmitted Arbitration lost in NOT ACK bit APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA Load SLA+R Load SLA+R or Load SLA+W No S1DAT action or No S1DAT action X X X 0 1 0 0 1 0 1 TO S1CON STO 0 0 0 0 0 0 0 0 1 1 SI 0 0 0 0 0 0 0 0 0 0 AA X X X X X 0 1 X X X SLA+R will be transmitted; ACK bit will be received As above SLA+W will be transmitted; SIO1 will be switched to MST/TRX mode I2C bus will be released; SIO1 will enter a slave mode A START condition will be transmitted when the bus becomes free Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned Repeated START condition will be transmitted STOP condition will be transmitted; STO flag will be reset STOP condition followed by a START condition will be transmitted; STO flag will be reset NEXT ACTION TAKEN BY SIO1 HARDWARE
38H
40H
SLA+R has been transmitted; ACK has b id been received SLA+R has been transmitted; NOT ACK t itt d has been received
No S1DAT action or no S1DAT action No S1DAT action or no S1DAT action or no S1DAT action
48H
50H
Data byte has been received; ACK has been d returned Data byte has been received; NOT ACK h id has been returned
Read data byte or read data byte Read data byte or read data byte or read data byte
0 0 1 0 1
0 0 0 1 1
0 0 0 0 0
0 1 X X X
58H
2003 Jan 28
45
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 8.
STATUS CODE (S1STA) 60H
Slave Receiver Mode
STATUS OF THE I2C BUS AND SIO1 HARDWARE Own SLA+W has been received; ACK hb d has been returned Arbitration lost in SLA+R/W as master; Own SLA+W has b id been received, ACK returned General call address (00H) has been received; ACK has received been returned Arbitration lost in SLA+R/W as master; General call address has been received, received ACK has been returned Previously addressed with own SLV address; DATA has b id been received; ACK has been returned Previously addressed with own SLA; DATA b byte h b has been received; NOT ACK has been returned APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA No S1DAT action or no S1DAT action No S1DAT action or X X X TO S1CON STO 0 0 0 SI 0 0 0 AA 0 1 0 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE
68H
no S1DAT action No S1DAT action or no S1DAT action No S1DAT action or
X X X X
0 0 0 0
0 0 0 0
1 0 1 0
70H
78H
no S1DAT action Read data byte or
X X
0 0
0 0
1 0
80H
read data byte Read data byte or read data byte or
X 0 0
0 0 0
0 0 0
1 0 1
88H
read data byte or
1
0
0
0
read data byte
1
0
0
1
90H
Previously addressed with General Call; DATA byte has been received; ACK h id has been returned Previously addressed with General Call; DATA b hb byte has been received; NOT ACK has been returned
Read data byte or
X
0
0
0
read data byte Read data byte or read data byte or
X 0 0
0 0 0
0 0 0
1 0 1
98H
read data byte or
1
0
0
0
read data byte
1
0
0
1
2003 Jan 28
46
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 8.
STATUS CODE (S1STA) A0H
Slave Receiver Mode (Continued)
STATUS OF THE I2C BUS AND SIO1 HARDWARE A STOP condition or repeated START di i has been condition h b received while still addressed as SLV/REC or SLV/TRX APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA No STDAT action or No STDAT action or 0 0 TO S1CON STO 0 0 SI 0 0 AA 0 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE
No STDAT action or
1
0
0
0
No STDAT action
1
0
0
1
Table 9.
STATUS CODE (S1STA) A8H
Slave Transmitter Mode
STATUS OF THE I2C BUS AND SIO1 HARDWARE Own SLA+R has been received; ACK hb d has been returned Arbitration lost in SLA+R/W as master; Own SLA+R has been received, ACK has been returned Data byte in S1DAT has been transmitted; ACK has been received Data byte in S1DAT has been transmitted; NOT ACK h b has been received APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA Load data byte or load data byte Load data byte or X X X TO S1CON STO 0 0 0 SI 0 0 0 AA 0 1 0 Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted; ACK bit will be received Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. Switched to not addressed SLV mode; no recognition of own SLA or General call address Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1 Switched to not addressed SLV mode; no recognition of own SLA or General call address. A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode; Own SLA will be recognized; General call address will be recognized if S1ADR.0 = logic 1. A START condition will be transmitted when the bus becomes free. NEXT ACTION TAKEN BY SIO1 HARDWARE
B0H
load data byte Load data byte or load data byte No S1DAT action or no S1DAT action or
X X X 0 0
0 0 0 0 0
0 0 0 0 0
1 0 1 01 1
B8H
C0H
no S1DAT action or
1
0
0
0
no S1DAT action
1
0
0
1
C8H
Last data byte in S1DAT has been id 0) transmitted (AA = 0); ACK has been received
No S1DAT action or no S1DAT action or
0 0
0 0
0 0
0 1
no S1DAT action or
1
0
0
0
no S1DAT action
1
0
0
1
2003 Jan 28
47
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 10.
STATUS CODE (S1STA) F8H
Miscellaneous States
STATUS OF THE I2C BUS AND SIO1 HARDWARE APPLICATION SOFTWARE RESPONSE TO/FROM S1DAT STA No S1DAT action TO S1CON STO SI AA Wait or proceed current transfer NEXT ACTION TAKEN BY SIO1 HARDWARE
No relevant state information available; SI = 0 Bus error during MST or selected slave modes, due to an illegal START or STOP condition. State 00H can also occur when interference causes SIO1 to enter an undefined state.
No S1CON action
00H
No S1DAT action
0
1
0
X
Only the internal hardware is affected in the MST or addressed SLV modes. In all cases, the bus is released and SIO1 is switched to the not addressed SLV mode. STO is reset.
Slave Transmitter Mode: In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 43). Data transfer is initialized as in the slave receiver mode. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be "1" (R) for SIO1 to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in Table 9. The slave transmitter mode may also be entered if arbitration is lost while SIO1 is in the master mode (see state B0H). If the AA bit is reset during a transfer, SIO1 will transmit the last byte of the transfer and enter state C0H or C8H. SIO1 is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all 1s as serial data. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C bus. Miscellaneous States: There are two S1STA codes that do not correspond to a defined SIO1 hardware state (see Table 10). These are discussed below. S1STA = F8H: This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when SIO1 is not involved in a serial transfer. S1STA = 00H: This status code indicates that a bus error has occurred during an SIO1 serial transfer. A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. A bus error may also be caused when external interference disturbs the internal SIO1 signals. When a bus error occurs, SI is set. To recover from a bus error, the STO flag must be set and SI must be cleared. This causes SIO1 to enter the "not addressed" slave mode (a defined state) and to clear the STO flag (no other bits in S1CON are affected). The
SDA and SCL lines are released (a STOP condition is not transmitted). Some Special Cases: The SIO1 hardware has facilities to handle the following special cases that may occur during a serial transfer: Simultaneous Repeated START Conditions from Two Masters A repeated START condition may be generated in the master transmitter or master receiver modes. A special case occurs if another master simultaneously generates a repeated START condition (see Figure 44). Until this occurs, arbitration is not lost by either master since they were both transmitting the same data. If the SIO1 hardware detects a repeated START condition on the I2C bus before generating a repeated START condition itself, it will release the bus, and no interrupt request is generated. If another master frees the bus by generating a STOP condition, SIO1 will transmit a normal START condition (state 08H), and a retry of the total serial data transfer can commence. DATA TRANSFER AFTER LOSS OF ARBITRATION Arbitration may be lost in the master transmitter and master receiver modes (see Figure 36). Loss of arbitration is indicated by the following states in S1STA; 38H, 68H, 78H, and B0H (see Figures 40 and 41). If the STA flag in S1CON is set by the routines which service these states, then, if the bus is free again, a START condition (state 08H) is transmitted without intervention by the CPU, and a retry of the total serial transfer can commence. FORCED ACCESS TO THE I2C BUS In some applications, it may be possible for an uncontrolled source to cause a bus hang-up. In such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between SDA and SCL. If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted. The SIO1 hardware behaves as if a STOP condition was received and is able to transmit a START condition. The STO flag is cleared by hardware (see Figure 45).
2003 Jan 28
48
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
S
SLA
W
A
DATA
A
S
BOTH MASTERS CONTINUE WITH SLA TRANSMISSION
08H
18H
28H
OTHER MASTER SENDS REPEATED START CONDITION EARLIER
SU00975
Figure 44. Simultaneous Repeated START Conditions from 2 Masters
TIME OUT
STA FLAG
SDA LINE
SCL LINE
START CONDITION
SU00976
Figure 45. Forced Access to a Busy I2C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA An I2C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the SIO1 hardware cannot resolve this type of problem. When this occurs, the problem must be resolved by the device that is pulling the SCL bus line LOW. If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the SCL line (see Figure 46). The SIO1 hardware transmits additional clock pulses when the STA flag is set, but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free. The SIO1 hardware attempts to generate a START condition after every two additional clock pulses on the SCL line. When the SDA line is eventually released, a normal START condition is transmitted, state 08H is entered, and the serial transfer continues. If a forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO1
I2 C
Bus
hardware performs the same action as described above. In each case, state 08H is entered after a successful START condition is transmitted and normal serial transfer continues. Note that the CPU is not involved in solving these bus hang-up problems. BUS ERROR A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. The SIO1 hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. When a bus error is detected, SIO1 immediately switches to the not addressed slave mode, releases the SDA and SCL lines, sets the interrupt flag, and loads the status register with 00H. This status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 10.
2003 Jan 28
49
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
STA FLAG (2) SDA LINE (1) (1) (3)
SCL LINE
START CONDITION
(1) Unsuccessful attempt to send a Start condition (2) SDA line released (3) Successful attempt to send a Start condition; state 08H is entered
SU00977
Figure 46. Recovering from a Bus Obstruction Caused by a Low Level on SDA Software Examples of SIO1 Service Routines: This section consists of a software example for: - Initialization of SIO1 after a RESET - Entering the SIO1 interrupt routine - The 26 state service routines for the - Master transmitter mode - Master receiver mode - Slave receiver mode - Slave transmitter mode INITIALIZATION In the initialization routine, SIO1 is enabled for both master and slave modes. For each mode, a number of bytes of internal data RAM are allocated to the SIO to act as either a transmission or reception buffer. In this example, 8 bytes of internal data RAM are reserved for different purposes. The data memory map is shown in Figure 47. The initialization routine performs the following functions: - S1ADR is loaded with the part's own slave address and the general call bit (GC) - P1.6 and P1.7 bit latches are loaded with logic 1s - RAM location HADD is loaded with the high-order address byte of the service routines - The SIO1 interrupt enable and interrupt priority bits are set - The slave mode is enabled by simultaneously setting the ENS1 and AA bits in S1CON and the serial clock frequency (for master modes) is defined by loading CR0 and CR1 in S1CON. The master routines must be started in the main program. The SIO1 hardware now begins checking the I2C bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and S1STA is loaded with the appropriate state information. The following text describes a fast method of branching to the appropriate service routine. SIO1 INTERRUPT ROUTINE When the SIO1 interrupt is entered, the PSW is first pushed on the stack. Then S1STA and HADD (loaded with the high-order address byte of the 26 service routines by the initialization routine) are pushed on to the stack. S1STA contains a status code which is the lower byte of one of the 26 service routines. The next instruction is RET, which is the return from subroutine instruction. When this instruction is executed, the high and low order address bytes are popped from stack and loaded into the program counter. The next instruction to be executed is the first instruction of the state service routine. Seven bytes of program code (which execute in eight machine cycles) are required to branch to one of the 26 state service routines. SI PUSH PSW PUSH S1STA PUSH HADD RET Save PSW Push status code (low order address byte) Push high order address byte Jump to state service routine
The state service routines are located in a 256-byte page of program memory. The location of this page is defined in the initialization routine. The page can be located anywhere in program memory by loading data RAM register HADD with the page number. Page 01 is chosen in this example, and the service routines are located between addresses 0100H and 01FFH. THE STATE SERVICE ROUTINES The state service routines are located 8 bytes from each other. Eight bytes of code are sufficient for most of the service routines. A few of the routines require more than 8 bytes and have to jump to other locations to obtain more bytes of code. Each state routine is part of the SIO1 interrupt routine and handles one of the 26 states. It ends with a RETI instruction which causes a return to the main program.
2003 Jan 28
50
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
SPECIAL FUNCTION REGISTERS
S1ADR S1DAT S1STA S1CON CR2 ENS1 STA ST0 SI 0 AA 0 CR!
GC
DB DA
0 CR0
D9 D8
PSW
D0
IPO
PS1
B8
IEN0
EA
ES1
AB
P1
P1.7
P1.6
90
80
INTERNAL DATA RAM 7F
BACKUP NUMBYTMST SLA HADD
ORIGINAL VALUE OF NUMBYTMST NUMBER OF BYTES AS MASTER SLA+R/W TO BE TRANSMITTED TO SLA HIGHER ADDRESS BYTE INTERRUPT ROUTINE SLAVE TRANSMITTER DATA RAM
53 52 51 50 4F
STD SLAVE RECEIVER DATA RAM SRD MASTER RECEIVER DATA RAM MRD MASTER TRANSMITTER DATA RAM MTD
48
40
38
30
R1 R0
19 18
00
SU00978
Figure 47. SIO1 Data Memory Map
2003 Jan 28
51
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
MASTER TRANSMITTER AND MASTER RECEIVER MODES The master mode is entered in the main program. To enter the master transmitter mode, the main program must first load the internal data RAM with the slave address, data bytes, and the number of data bytes to be transmitted. To enter the master receiver mode, the main program must first load the internal data RAM with the slave address and the number of data bytes to be received. The R/W bit determines whether SIO1 operates in the master transmitter or master receiver mode. Master mode operation commences when the STA bit in S1CION is set by the SETB instruction and data transfer is controlled by the master state service routines in accordance with Table 6, Table 7, Figure 40, and Figure 41. In the example below, 4 bytes are transferred. There is no repeated START condition. In the event of lost arbitration, the transfer is restarted when the bus becomes free. If a bus error occurs, the I2C bus is released and SIO1 enters the not selected slave receiver mode. If a slave device returns a not acknowledge, a STOP condition is generated. A repeated START condition can be included in the serial transfer if the STA flag is set instead of the STO flag in the state service routines vectored to by status codes 28H and 58H. Additional software must be written to determine which data is transferred after a repeated START condition. SLAVE TRANSMITTER AND SLAVE RECEIVER MODES After initialization, SIO1 continually tests the I2C bus and branches to one of the slave state service routines if it detects its own slave address or the general call address (see Table 8, Table 9, Figure 42, and Figure 43). If arbitration was lost while in the master mode, the master mode is restarted after the current transfer. If a bus error occurs, the I2C bus is released and SIO1 enters the not selected slave receiver mode.
In the slave receiver mode, a maximum of 8 received data bytes can be stored in the internal data RAM. A maximum of 8 bytes ensures that other RAM locations are not overwritten if a master sends more bytes. If more than 8 bytes are transmitted, a not acknowledge is returned, and SIO1 enters the not addressed slave receiver mode. A maximum of one received data byte can be stored in the internal data RAM after a general call address is detected. If more than one byte is transmitted, a not acknowledge is returned and SIO1 enters the not addressed slave receiver mode. In the slave transmitter mode, data to be transmitted is obtained from the same locations in the internal data RAM that were previously loaded by the main program. After a not acknowledge has been returned by a master receiver device, SIO1 enters the not addressed slave mode. ADAPTING THE SOFTWARE FOR DIFFERENT APPLICATIONS The following software example shows the typical structure of the interrupt routine including the 26 state service routines and may be used as a base for user applications. If one or more of the four modes are not used, the associated state service routines may be removed but, care should be taken that a deleted routine can never be invoked. This example does not include any time-out routines. In the slave modes, time-out routines are not very useful since, in these modes, SIO1 behaves essentially as a passive device. In the master modes, an internal timer may be used to cause a time-out if a serial transfer is not complete after a defined period of time. This time period is defined by the system connected to the I2C bus.
2003 Jan 28
52
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
00D8 00D9 00DA 00DB 00A8 00B8
!******************************************************************************************************** ! SI01 EQUATE LIST !******************************************************************************************************** !******************************************************************************************************** ! LOCATIONS OF THE SI01 SPECIAL FUNCTION REGISTERS !******************************************************************************************************** S1CON -0xd8 S1STA -0xd9 S1DAT -0xda S1ADR -0xdb IEN0 IP0 -0xa8 -02b8
!******************************************************************************************************** ! BIT LOCATIONS !******************************************************************************************************** 00DD 00BD STA SI01HP -0xdd -0xbd ! STA bit in S1CON ! IP0, SI01 Priority bit
00D5 00C5 00C1 00E5
!******************************************************************************************************** ! IMMEDIATE DATA TO WRITE INTO REGISTER S1CON !******************************************************************************************************** ENS1_NOTSTA_STO_NOTSI_AA_CR0 -0xd5 ! Generates STOP ! (CR0 = 100 kHz) ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 -0xc5 ! Releases BUS and ! ACK ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 -0xc1 ! Releases BUS and ! NOT ACK ENS1_STA_NOTSTO_NOTSI_AA_CR0 -0xe5 ! Releases BUS and ! set STA !******************************************************************************************************** ! GENERAL IMMEDIATE DATA !******************************************************************************************************** OWNSLA -0x31 ! Own SLA+General Call ! must be written into S1ADR ENSI01 -0xa0 ! EA+ES1, enable SIO1 interrupt ! must be written into IEN0 PAG1 -0x01 ! select PAG1 as HADD SLAW -0xc0 ! SLA+W to be transmitted SLAR -0xc1 ! SLA+R to be transmitted SELRB3 -0x18 ! Select Register Bank 3 !******************************************************************************************************** ! LOCATIONS IN DATA RAM !******************************************************************************************************** MTD -0x30 ! MST/TRX/DATA base address MRD -0x38 ! MST/REC/DATA base address SRD -0x40 ! SLV/REC/DATA base address STD -0x48 ! SLV/TRX/DATA base address BACKUP NUMBYTMST SLA HADD -0x53 -0x52 -0x51 -0x50 ! Backup from NUMBYTMST ! To restore NUMBYTMST in case ! of an Arbitration Loss. ! Number of bytes to transmit ! or receive as MST. ! Contains SLA+R/W to be ! transmitted. ! High Address byte for STATE 0 ! till STATE 25.
0031 00A0 0001 00C0 00C1 0018
0030 0038 0040 0048 0053 0052 0051 0050
2003 Jan 28
53
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
0000
4100
!******************************************************************************************************** ! INITIALIZATION ROUTINE ! Example to initialize IIC Interface as slave receiver or slave transmitter and ! start a MASTER TRANSMIT or a MASTER RECEIVE function. 4 bytes will be transmitted or received. !******************************************************************************************************** .sect strt .base 0x00 ajmp INIT ! RESET .sect .base INIT: initial 0x200 mov setb setb mov orl clr mov S1ADR,#OWNSLA ! Load own SLA + enable ! general call recognition ! P1.6 High level. ! P1.7 High level.
0200 0203 0205 0207 020A 020D 020F
75DB31 D296 D297 755001 43A8A0 C2BD 75D8C5
P1(6) P1(7) HADD,#PAG1 IEN0,#ENSI01 ! Enable SI01 interrupt SI01HP ! SI01 interrupt low priority S1CON, #ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! Initialize SLV funct.
!******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! START MASTER TRANSMIT FUNCTION !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0212 0215 0218 755204 7551C0 D2DD mov mov setb NUMBYTMST,#0x4 SLA,#SLAW STA ! Transmit 4 bytes. ! SLA+W, Transmit funct. ! set STA in S1CON
021A 021D 0220
755204 7551C1 D2DD
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! START MASTER RECEIVE FUNCTION !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - mov NUMBYTMST,#0x4 ! Receive 4 bytes. mov SLA,#SLAR ! SLA+R, Receive funct. setb STA ! set STA in S1CON
!******************************************************************************************************** ! SI01 INTERRUPT ROUTINE !******************************************************************************************************** .sect intvec ! SI01 interrupt vector .base 0x00 ! S1STA and HADD are pushed onto the stack. ! They serve as return address for the RET instruction. ! The RET instruction sets the Program Counter to address HADD, ! S1STA and jumps to the right subroutine. 002B 002D 002F 0031 C0D0 C0D9 C050 22 push psw push S1STA push HADD ret ! save psw
! JMP to address HADD,S1STA.
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 00, Bus error. ! ACTION : Enter not addressed SLV mode and release bus. STO reset. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect st0 .base 0x100 0100 0103 0105 75D8D5 D0D0 32 mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI ! set STO,AA psw
2003 Jan 28
54
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!******************************************************************************************************** !******************************************************************************************************** ! MASTER STATE SERVICE ROUTINES !******************************************************************************************************** ! State 08 and State 10 are both for MST/TRX and MST/REC. ! The R/W bit decides whether the next state is within ! MST/TRX mode or within MST/REC mode. !******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 08, A, START condition has been transmitted. ! ACTION : SLA+R/W are transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts8 .base 0x108 0108 010B 010E 8551DA 75D8C5 01A0 S1DAT,SLA ! Load SLA+R/W S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI ajmp INITBASE1 !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 10, A repeated START condition has been ! transmitted. ! ACTION : SLA+R/W are transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts10 .base 0x110 0110 0113 010E 8551DA 75D8C5 01A0 .sect ibase1 .base 0xa0 INITBASE1: S1DAT,SLA ! Load SLA+R/W S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI ajmp INITBASE1 mov mov mov mov
00A0 00A3 00A5 00A7 00AA 00AC
75D018 7930 7838 855253 D0D0 32
mov mov mov mov pop reti
psw,#SELRB3 r1,#MTD r0,#MRD BACKUP,NUMBYTMST psw
! Save initial value
!******************************************************************************************************** !******************************************************************************************************** ! MASTER TRANSMITTER STATE SERVICE ROUTINES !******************************************************************************************************** !******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 18, Previous state was STATE 8 or STATE 10, SLA+W have been transmitted, ! ACK has been received. ! ACTION : First DATA is transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts18 .base 0x118 0118 011B 011D 75D018 87DA 01B5 mov psw,#SELRB3 mov S1DAT,@r1 ajmp CON
2003 Jan 28
55
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 20, SLA+W have been transmitted, NOT ACK has been received ! ACTION : Transmit STOP condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts20 .base 0x120 0120 0123 0125 75D8D5 D0D0 32 mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 28, DATA of S1DAT have been transmitted, ACK received. ! ACTION : If Transmitted DATA is last DATA then transmit a STOP condition, ! else transmit next DATA. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts28 .base 0x128 0128 012B 012E D55285 75D8D5 01B9 .sect mts28sb .base 0x0b0 NOTLDAT1: CON: djnz mov NUMBYTMST,NOTLDAT1 ! JMP if NOT last DATA S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! clr SI, set AA ajmp RETmt
00B0 00B3 00B5 00B8 00B9 00BB
75D018 87DA 75D8C5 09 D0D0 32
mov mov mov
RETmt
inc pop reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 30, DATA of S1DAT have been transmitted, NOT ACK received. ! ACTION : Transmit a STOP condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts30 .base 0x130 : mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw
psw,#SELRB3 S1DAT,@r1 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r1 psw
0130 0133 0135
75D8D5 D0D0 32
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 38, Arbitration lost in SLA+W or DATA. ! ACTION : Bus is released, not addressed SLV mode is entered. ! A new START condition is transmitted when the IIC bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts38 .base 0x138 0138 013B 013E 75D8E5 855352 01B9 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov NUMBYTMST,BACKUP ajmp RETmt
2003 Jan 28
56
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!******************************************************************************************************** !******************************************************************************************************** ! MASTER RECEIVER STATE SERVICE ROUTINES !******************************************************************************************************** !******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 40, Previous state was STATE 08 or STATE 10, ! SLA+R have been transmitted, ACK received. ! ACTION : DATA will be received, ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts40 .base 0x140 0140 0143 75D8C5 D0D0 32 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr STA, STO, SI set AA psw
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 48, SLA+R have been transmitted, NOT ACK received. ! ACTION : STOP condition will be generated. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mts48 .base 0x148 0148 014B 014D 75D8D5 D0D0 32 STOP: mov pop reti S1CON,#ENS1_NOTSTA_STO_NOTSI_AA_CR0 ! set STO, clr SI psw
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 50, DATA have been received, ACK returned. ! ACTION : Read DATA of S1DAT. ! DATA will be received, if it is last DATA then NOT ACK will be returned else ACK will be returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mrs50 .base 0x150 0150 0153 0155 75D018 A6DA 01C0 .sect .base 00C0 00C3 00C6 00C8 00CB 00CC 00CE D55205 75D8C1 8003 75D8C5 08 D0D0 32 REC1: mrs50s 0xc0 djnz mov NUMBYTMST,NOTLDAT2 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 ! clr SI,AA sjmp RETmr mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA inc r0 pop psw reti mov psw,#SELRB3 mov @r0,S1DAT ajmp REC1
! Read received DATA
NOTLDAT2: RETmr:
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 58, DATA have been received, NOT ACK returned. ! ACTION : Read DATA of S1DAT and generate a STOP condition. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect mrs58 .base 0x158 0158 015B 015D 75D018 A6DA 80E9 mov psw,#SELRB3 mov @R0,S1DAT sjmp STOP 57
2003 Jan 28
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!******************************************************************************************************** !******************************************************************************************************** ! SLAVE RECEIVER STATE SERVICE ROUTINES !******************************************************************************************************** !******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 60, Own SLA+W have been received, ACK returned. ! ACTION : DATA will be received and ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs60 .base 0x160 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA mov psw,#SELRB3 ajmp INITSRD .sect insrd .base 0xd0 INITSRD: mov mov pop reti r0,#SRD r1,#8 psw
0160 0163 0166
75D8C5 75D018 01D0
00D0 00D2 00D4 00D6
7840 7908 D0D0 32
0168 016B 016E
75D8E5 75D018 01D0
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 68, Arbitration lost in SLA and R/W as MST ! Own SLA+W have been received, ACK returned ! ACTION : DATA will be received and ACK returned. ! STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs68 .base 0x168 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov psw,#SELRB3 ajmp INITSRD !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 70, General call has been received, ACK returned. ! ACTION : DATA will be received and ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs70 .base 0x170 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA mov psw,#SELRB3 ! Initialize SRD counter ajmp initsrd !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 78, Arbitration lost in SLA+R/W as MST. ! General call has been received, ACK returned. ! ACTION : DATA will be received and ACK returned. ! STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs78 .base 0x178 mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 mov psw,#SELRB3 ! Initialize SRD counter ajmp INITSRD
0170 0173 0176
75D8C5 75D018 01D0
0178 017B 017E
75D8E5 75D018 01D0
2003 Jan 28
58
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 80, Previously addressed with own SLA. DATA received, ACK returned. ! ACTION : Read DATA. ! IF received DATA was the last ! THEN superfluous DATA will be received and NOT ACK returned ELSE next DATA will be received and ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs80 .base 0x180 0180 0183 0185 75D018 A6DA 01D8 .sect .base 00D8 00DA 00DD 00DF 00E0 00E3 00E4 00E6 D906 75D8C1 D0D0 32 75D8C5 08 D0D0 32 REC2: LDAT: srs80s 0xd8 djnz mov pop reti mov inc pop reti r1,NOTLDAT3 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_NOTAA_CR0 ! clr SI,AA psw S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r0 psw mov psw,#SELRB3 mov @r0,S1DAT ajmp REC2
! Read received DATA
NOTLDAT3:
RETsr:
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 88, Previously addressed with own SLA. DATA received NOT ACK returned. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. ! Recognition of own SLA. General call recognized, if S1ADR. 0-1. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs88 .base 0x188 0188 018B 75D8C5 01E4 S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA ajmp RETsr !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 90, Previously addressed with general call. ! DATA has been received, ACK has been returned. ! ACTION : Read DATA. After General call only one byte will be received with ACK ! the second DATA will be received with NOT ACK. ! DATA will be received and NOT ACK returned. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs90 .base 0x190 0190 0193 0195 75D018 A6DA 01DA mov psw,#SELRB3 mov @r0,S1DAT ! Read received DATA ajmp LDAT !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : 98, Previously addressed with general call. ! DATA has been received, NOT ACK has been returned. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. Recognition of own SLA. General call recognized, if S1ADR. 0-1. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srs98 .base 0x198 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw mov
0198 019B 019D
75D8C5 D0D0 32
2003 Jan 28
59
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : A0, A STOP condition or repeated START has been received, ! while still addressed as SLV/REC or SLV/TRX. ! ACTION : No save of DATA, Enter NOT addressed SLV mode. ! Recognition of own SLA. General call recognized, if S1ADR. 0-1. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect srsA0 .base 0x1a0 01A0 01A3 01A5 75D8C5 D0D0 32 mov pop reti S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA psw
!******************************************************************************************************** !******************************************************************************************************** ! SLAVE TRANSMITTER STATE SERVICE ROUTINES !******************************************************************************************************** !******************************************************************************************************** !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : A8, Own SLA+R received, ACK returned. ! ACTION : DATA will be transmitted, A bit received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsa8 .base 0x1a8 01A8 01AB 01AE 8548DA 75D8C5 01E8 .sect ibase2 .base 0xe8 INITBASE2: S1DAT,STD ! load DATA in S1DAT S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA ajmp INITBASE2 mov mov
00E8 00EB 00ED 00EE 00F0
75D018 7948 09 D0D0 32
mov mov inc pop reti
psw,#SELRB3 r1, #STD r1 psw
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : B0, Arbitration lost in SLA and R/W as MST. Own SLA+R received, ACK returned. ! ACTION : DATA will be transmitted, A bit received. ! STA is set to restart MST mode after the bus is free again. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsb0 .base 0x1b0 01B0 01B3 01B6 8548DA 75D8E5 01E8 mov S1DAT,STD ! load DATA in S1DAT mov S1CON,#ENS1_STA_NOTSTO_NOTSI_AA_CR0 ajmp INITBASE2
2003 Jan 28
60
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
01B8 01BB 01BD
75D018 87DA 01F8
!- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : B8, DATA has been transmitted, ACK received. ! ACTION : DATA will be transmitted, ACK bit is received. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsb8 .base 0x1b8 mov psw,#SELRB3 mov S1DAT,@r1 ajmp SCON .sect .base scn 0xf8 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA r1 psw
00F8 00FB 00FC 00FE
75D8C5 09 D0D0 32
SCON:
01C0 01C3 01C5
75D8C5 D0D0 32
inc pop reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : C0, DATA has been transmitted, NOT ACK received. ! ACTION : Enter not addressed SLV mode. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsc0 .base 0x1c0 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA pop psw reti !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ! STATE : C8, Last DATA has been transmitted (AA=0), ACK received. ! ACTION : Enter not addressed SLV mode. !- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .sect stsc8 .base 0x1c8 mov S1CON,#ENS1_NOTSTA_NOTSTO_NOTSI_AA_CR0 ! clr SI, set AA pop psw reti
01C8 01CB 01CD
75D8C5 D0D0 32
!******************************************************************************************************** !******************************************************************************************************** ! END OF SI01 INTERRUPT ROUTINE !******************************************************************************************************** !********************************************************************************************************
2003 Jan 28
61
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Storage temperature range Voltage on EA/VPP to VSS Voltage on any other pin to VSS Input, output DC current on any single I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING -65 to +150 -0.5 to +13 -0.5 to +6.5 5.0 1.0 UNIT C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
2003 Jan 28
62
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) TYPE MIN P87C554 SBBD P87C554 SFBD 2.7 3.0 MAX 5.5 5.5 MIN 0 0 MAX 8 8 MIN 4.5 V 4.5 V MAX 5.5 V 5.5 V MIN 0 0 MAX 16 16 FREQUENCY (MHz) SUPPLY VOLTAGE (V) FREQUENCY (MHz) TE PE TU E TEMPERATURE RANGE (C), Tamb E 0 to +70 -40 to +85
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0 V; VDD and Tamb minimum and maximum, per device specifications table. SYMBOL PARAMETER TEST CONDITIONS See notes 1 and 2 fOSC = 8 MHz fOSC = 16 MHz See notes 1 and 3 fOSC = 8 MHz fOSC = 16 MHz See notes 1 and 4; 2 V < VPD < VDD max -0.5 -0.5 -0.5 0.2VDD+0.9 0.7 VDD 0.7 VDD VIN = 0.45 V See note 6 0.45 V < VI < VDD 0 V < VI < 6 V 0 V < VDD < 5.5 V 0.45 V < VI < VDD 0.45 V < Vin < VDD IOL = 1.6 mA7 IOL = 3.2 mA7 IOL = 3.0 mA7 VCC - 0.7 07 VCC - 0.7 07 VCC - 0.7 2.4 0.8 VDD 40 Test freq = 1 MHz, Tamb = 25C AVDD = VDD0.2 V Port 5 = 0 to AVDD 2 V < AVPD < AVDD max 2.7 225 10 VCC = 2.7 V IOH = -20 A VCC = 4.5 IOH = -30 A VOH1 VOH2 RRST CIO Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)8 Output high voltage (RST) Internal reset pull-down resistor Pin capacitance VCC = 2.7 V IOH = -3.2 mA -IOH = 400 A -IOH = 120 A LIMITS MIN MAX 16 32 4 8 50 UNIT
IDD
Supply current operating
mA
IID IPD Inputs VIL VIL1 VIL2 VIH VIH1 VIH2 IIL ITL IIL1 IIL2 IIL3 IIL4 Outputs VOL VOL1 VOL2 VOH
Idle mode Power-down current
mA A
Input low voltage, except EA, P1.6, P1.7 Input low voltage to EA Input low voltage to P1.6/SCL, P1.7/SDA5 Input high voltage, except XTAL1, RST Input high voltage, XTAL1, RST Input high voltage, P1.6/SCL, P1.7/SDA5 Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 Input leakage current, port 0, EA, STADC, EW Input leakage current, P1.6/SCL, P1.7/SDA Input leakage current, port 5 Input leakage current, ports 1, 2, 3, 4 in high impedance mode Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA
0.2VDD-0.1 0.2VDD-0.3 0.3VDD VDD+0.5 VDD+0.5 6.0 -50 -650 10 10 1 10 0.4 0.4 0.4
V V V V V V A A A A A A V V V V V V V V k pF
Analog Inputs AVDD AIDD AIID AIPD Analog supply voltage: 87C5549 Analog supply current: operating: Idle mode: 87C554 Power-down mode: 87C554 5.5 1.2 50 50 V mA A A
2003 Jan 28
63
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
DC ELECTRICAL CHARACTERISTICS (Continued)
VDD and Tamb minimum and maximum, per device specifications table. TEST SYMBOL Analog Inputs (Continued) AVIN AVREF Analog input voltage Reference voltage: AVREF- AVREF+ Resistance between AVREF+ and AVREF- Analog input capacitance Sampling time (10 bit mode) Sampling time (8 bit mode) Conversion time (including sampling time, 10 bit mode) Conversion time (including sampling time, 8 bit mode) Differential non-linearity10, 11, 12 Integral non-linearity10, 13 (10 bit mode) Integral non-linearity (8 bit mode) Offset error10, 14 (10 bit mode) AVSS-0.2 AVSS-0.2 AVDD+0.2 10 50 15 8tCY 5tCY 50tCY 24tCY 1 2 1 2 1 0.4 error10, 16 517, 18 3 1 0-100 kHz -60 AVDD+0.2 V V V k pF s s s s LSB LSB LSB LSB LSB % LSB LSB dB PARAMETER CONDITIONS MIN LIMITS MAX UNIT
RREF CIA tADS tADS8 tADC tADC8 DLe ILe ILe8 OSe OSe8 Ge Ae MCTC Ct
Offset error (8 bit mode) Gain error10, 15
Absolute voltage
Channel to channel matching Crosstalk between inputs of port
NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 57 through 61 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. 6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address bits are stabilizing. 9. The following condition must not be exceeded: VDD - 0.2 V < AVDD < VDD + 0.2 V. 10. Conditions: AVREF- = 0 V; AVDD = 5.0 V. Measurement by continuous conversion of AVIN = -20 mV to 5.12 V in steps of 0.5 mV, deriving parameters from collected conversion results of ADC. AVREF+ (87C554) = 5.12 V. ADC is monotonic with no missing codes. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 48.) 12. The ADC is monotonic; there are no missing codes. 13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 48.) 14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 48.) 15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 48.) 16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 17. This should be considered when both analog and digital signals are simultaneously input to port 5. 18. This parameter is guaranteed by design and characterized, but is not production tested.
2003 Jan 28
64
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Offset error OSe
Gain error Ge
1023
1022
1021
1020
1019
1018 (2)
7 Code Out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal)
0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
AVIN (LSBideal) Offset error OSe (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve.
1 LSB =
AVREF+
- AVREF-
1024
SU00212
Figure 48. ADC Conversion Characteristic
2003 Jan 28
65
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
AC ELECTRICAL CHARACTERISTICS
VDD and Tamb minimum and maximum, per device specifications table; VSS = 0 V; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified. 16 MHz CLOCK SYMBOL 1/fCLK tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX tXHDV FIGURE 49 49 49 49 49 49 49 49 49 49 49 49 50, 51 50, 51 50, 51 50, 51 50, 51 50, 51 50, 51 50, 51 50, 51 50, 51 51 50, 51 50, 51 50, 51 52 52 52 52 53 53 53 53 53 PARAMETER System clock frequency, see Note 1 ALE pulse width Address valid to ALE LOW Address hold after ALE LOW ALE LOW to valid instruction in ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN LOW to address float RD pulse width WR pulse width RD LOW to valid data in Data hold after RD Data float after RD ALE LOW to valid data in Address to valid data in ALE LOW to RD or WR LOW Address valid to RD low or WR LOW Data valid to WR transition Data hold after WR Data valid time WR HIGH RD LOW to address float RD or WR HIGH to ALE HIGH High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid 37.5 6.25 6.25 - 6.25 48.75 - 0 - - - 87.5 87.5 - 0 - - - 43.75 50 1.25 6.25 88.75 - 6.25 33.3 33.3 - - 500 179.5 32.5 0 - - - - 60 - - 33.75 - 6.25 76.25 10 - - 66.25 - 42.5 100 116.25 143.75 - - - - 0 56.25 50 50 20 20 - - - - 179.5 MIN MAX External Program Memory 3.5 tCLK-25 0.5 tCLK-25 0.5 tCLK-25 - 0.5 tCLK-25 1.5 tCLK-45 - 0 - - - 3 tCLK-100 3 tCLK-100 - 0 - - - 1.5 tCLK-50 2 tCLK-75 0.5 tCLK-30 0.5 tCLK-25 3.5 tCLK-130 - 0.5 tCLK-25 tCLK tCLK - - 6 tCLK 5 tCLK -133 tCLK-30 0 - 0.4 0.4 16 - - - 2 tCLK-65 - - 1.5 tCLK-60 - 0.5 tCLK-25 2.5 tCLK-80 10 - - 2.5 tCLK-90 - tCLK-20 4 tCLK-150 4.5 tCLK-165 1.5 tCLK+50 - - - - 0 0.5 tCLK+25 tCLK tCLK 20 20 - - - - 5 tCLK-133 0.6 0.6 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VARIABLE CLOCK MIN MAX UNIT
External Data Memory
External Clock
UART Timing - Shift Register Mode
2003 Jan 28
66
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Table 11. I2C-bus interface timing
All values referred to VIH(min) and VIL(max) levels; see Figure 565. I2C-BUS SYMBOL tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD tFD PARAMETER START condition hold time LOW period of the SCL clock HIGH period of the SCL clock Rise time of SCL signals Fall time of SCL signals Data set-up time SDA set-up time (before repeated START condition) SDA set-up time (before STOP condition) Data hold time Set-up time for a repeated START condition Set-up time for STOP condition Bus free time between Rise time of SDA signals Fall time of SDA signals INPUT 7 tCLK 8 tCLK 7 tCLK 1 s 0.3 s 250 ns 250 ns 250 ns 0 ns 7 tCLK 7 tCLK 7 tCLK 1 s 0.3 s OUTPUT > 4.0 s1 > 4.7 s1 > 4.0 s1 -2 < 0.3 s3 > 10 tCLK-tRD > 1 s1 > 4 tCLK > 4 tCLK-tFC > 4.7 s1 > 4.0 s1 > 4.7 s1 -2 < 0.3 s3
NOTES 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s. 3. Spikes of the SDA and SCL lines with a duration of less than 3 tCLK will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLK = 1/fCLK = one oscillator clock period at pin XTAL1. For 83 ns < tCLK < 285 ns (12 MHz > fCLK > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 5. These values are guaranteed but not 100% production tested. 6. See application note AN457 for external memory interface. 7. Parts are guaranteed to operate down to 0Hz.
2003 Jan 28
67
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 49. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 50. External Data Memory Read Cycle
2003 Jan 28
68
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
A0-A7 FROM RI OR DPL
tQVWX tDW
DATA OUT
tWHQX
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
SU00213
Figure 51. External Data Memory Write Cycle
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 52. External Clock Drive XTAL1
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 53. Shift Register Mode Timing
2003 Jan 28
69
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
2.4V 2.0V Test Points 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at 2.0V for a logic `1' and 0.8V for a logic `0'. 0.8V 2.0V
SU00215
Figure 54. AC Testing Input/Output
Float 2.4V 2.0V 0.8V 2.0V 0.8V 2.4V
0.45V
0.45V
NOTE: The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400A at the voltage test levels.
SU00216
Figure 55. AC Testing Input, Float Waveform
repeated START condition START or repeated START condition tRD STOP condition 0.7 VCC 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 tSU;STA START condition
SDA (INPUT/OUTPUT)
SCL (INPUT/OUTPUT)
SU00107A
Figure 56. Timing SIO1 (I2C) Interface
2003 Jan 28
70
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
32 28 24 ICC(mA) 20 16 12 8 4
MAXIMUM ACTIVE MODE
TYPICAL ACTIVE MODE
MAXIMUM IDLE MODE TYPICAL IDLE MODE
0 0 2 4 6 8 10 12 FREQ AT XTAL1 (MHz) 14 16
SU01471
Figure 57. 16 MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
VDD
VDD IDD P1.6 P1.7 VDD P0 EA EW VDD VDD
RST STADC (NC) CLOCK SIGNAL XTAL2 XTAL1
AVSS VSS AVref-
SU00218
Figure 58. IDD Test Condition, Active Mode All other pins are disconnected1 1. Active Mode: a. The following pins must be forced to VDD: EA, RST, Port 0, and EW. b. The following pins must be forced to VSS: STADC, AVss, and AVref-. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2003 Jan 28
71
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
VDD
VDD IDD P1.6 P1.7 RST STADC P0 VDD VDD
(NC) CLOCK SIGNAL
XTAL2 XTAL1
EW EA AVSS
VSS
AVref-
SU00219
Figure 59. IDD Test Condition, Idle Mode All other pins are disconnected2 2. Idle Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, AVss, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
VDD-0.5 0.5V
0.7VDD 0.2VDD-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00220
Figure 60. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5 ns
VDD P1.6 P1.7 RST STADC P0 VDD IDD VDD VDD
(NC)
XTAL2 XTAL1 VSS
EW EA AVSS AVref-
SU00221
Figure 61. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2 V to 5.5 V3 3. Power Down Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2003 Jan 28
72
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
EPROM CHARACTERISTICS
The 87C554 contains three signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C554 manufactured by Philips: (030H) = 15H indicates manufactured by Philips Components (031H) = 93H indicates 87C554 (60H) = 01H
Security Bits
With none of the security bits programmed the code in the program memory can be verified. When only security bit 1 (see Table 12) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.
Program Verification
If security bits 2 or 3 have not been programmed, the on-chip program memory can be read out for program verification.
Table 12. Program Security Bits for EPROM Devices
PROGRAM LOCK BITS1, 2 SB1 1 2 3 4 U P P P SB2 U U P P SB3 U U U P PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, external execution is disabled.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
2003 Jan 28
73
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
2003 Jan 28
74
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
REVISION HISTORY
Rev _5 Date 20030128 Description Product data (9397 750 11006); ECN 853-2408 29338 of 07 January 2003
* References to ROM (83) devices removed
_4 20001110 Preliminary data (9397 750 07505); previous release
Modifications:
2003 Jan 28
75
Philips Semiconductors
Product data
80C51 8-bit microcontroller - 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
80C554/87C554
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 01-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11006
Philips Semiconductors
2003 Jan 28 76

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